Considering the growing number of Internet and cloud computing data centers in operation today and the high, yet flexible data center electric load, data centers can be good candidates to offer ancillary services and respond to regulation signals in a smart grid. This paper considers a problem whereby the smart grid employs both day-ahead dynamic energy prices and regulation signals to incentivize (cloud) data centers to simultaneously reduce their energy consumptions and participate in an ancillary service market. A data center controller schedules task dispatch and performs resource allocation in order to minimize the overall cost, which is the total electricity cost based on time-of-use energy prices minus any monetary compensations that data center may receive due to offering ancillary services. Moreover, the data center must satisfy average latency requirements in processing requests as specified in service-level agreements with clients. A two-tier hierarchical solution is presented for the data center controller, which achieves optimality in minimizing the overall cost with polynomial time complexity. Experimental results on Google trace demonstrate the effectiveness of the proposed solution in minimizing the overall cost in the data center.
FinFET device has been proposed as a promising substitute for the traditional bulk CMOS-based device at the nanoscale, due to its extraordinary properties such as improved channel controllability, high ON/OFF current ratio, reduced short-channel effects, and relative immunity to gate line-edge roughness. In addition, the near-ideal subthreshold behavior indicates the potential application of FinFET circuits in the nearthreshold supply voltage regime, which consumes an order of magnitude less energy than the regular strong-inversion circuits operating in the super-threshold supply voltage regime. This paper presents a design flow of creating standard cells by using the FinFET 5nm technology node, including both near-threshold and super-threshold operations, and building a Liberty-format standard cell library. The circuit synthesis results of various combinational and sequential circuits based on the 5nm FinFET standard cell library show up to 40X circuit speed improvement and three orders of magnitude energy reduction compared to those of 45nm bulk CMOS technology.
There are hundreds of millions of tables in Web pages that contain useful information for many applications. Leveraging data within these tables is di cult because of the wide variety of structures, formats and data encoded in these tables. TabVec is an unsupervised method to embed tables into a vector space to support classi cation of tables into categories (entity, relational, matrix, list, and nondata) with minimal user intervention. TabVec deploys syntax and semantics of table cells, and embeds the structure of tables in a table vector space. This enables superior classi cation of tables even in the absence of domain annotations. Our evaluations in four real world domains show that TabVec improves classi cation accuracy by more than 20% compared to three state of the art systems, and that those systems require signi cant in domain training to achieve good results.
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