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Abstmct-Anovel, simple, and straightforward technology, FEWMNOS, for a high-packing-density LDD CMOS device, is described. A salicide polysilicon layer, termed a window pad, is used as a window etch stop, source/drain (S/D) diffusion source, and extra sublevel interconnection layer. The reductions in layout area in transistor and in many applications including memory and ASIC are significant.

In this paper a merged 2.5 V and 3.3 V high performance 0.25 pm CMOS ASIC technology is presented. This technology features a 50 8, gate oxide, n+-polysilicon gate, and 4/5 levels of metal. An improvement of 1.45X in circuit performance and 3.7X in packing density is achieved over our previous generation 0.35 pm CMOS technology by device scaling and aggressive design rules. The nominal ring oscillator delay time is 38 ps. INTRODUCTIONThis paper describes a merged 2.5 V and 3.3 V 0.25 pm CMOS technology where transistors with both voltage grades are integrated on the same chip with the addition of only one extra implant mask level. This approach allows the implementation of 2.5 V and 3.3 V functional blocks on the same chip. Furthermore, process technologies for each supply voltage grade need not be developed, transferred, or qualified for manufacturing separately. All transistors utilize a 50 8, S i 0 2 gate dielectric. Aggressive interconnect and isolation design rules are employed ,to achieve a factor of 3.7 and 5.7 improvement in packing density over our previous generation 0.35 p m [ l ] and 0.5 pm [2] CMOS technologies, respectively. Nominal gate delays of 38 ps for an unloaded ring oscillator is measured. These improvements in performance and packing density have been obtained through the use of (i) a scaled LOCOS isolation ( Fig. 1) scheme that allows the active area to tub edge separation to be reduced below 0.40 pm (Fig. 2), (ii) high energy implants to define the n and p tubs, (iii) a 50 8, gate oxide used for all transistors, (iv) hard-mask gate processing and deep-UV photolithography with Le# control of 3 0 = 0.04 pm, (v) 415 level metal routing with metal design rules optimized for ASIC applications (Fig. 3). THE PROCESSThe starting wafers consist of 5.0 pm p-epi grown on a (100) pf Si substrate. The isolation scheme used is a low cost scaled LOCOS process. Active areas are defined by patterning the LOCOS stack. Pad-Si02 and Si3N4 thickness as well as the field-oxide (FOX) growth conditions are optimized to achieve a birds beak length of 600 8, as shown in the SEM micrograph Fig. 1. The grown field-oxide thickness is 2500 A. We note that the encroachment of the field-oxide into the active areas (i.e., birds beak length) is mostly determined by the pad-Si02 thickness and the field-oxide growth conditions rather than the Si3 N4 thickness. No LOCOS stack lifting is observed after the field-oxide is grown. After nitride removal a sacrificiallscreen Si02 layer is grown. N-and P-tubs are formed by high energy implants. The use of high energy implant methodology reduces the total number of process steps as compared with conventional twin-tub flow [3]. The N-tub is defined by a deep phosphorus implant which determines the tub depth. Another shallower phosphorus implant serves as a channel-stop for the PMOS devices. Arsenic and BF, are implanted to set the threshold voltage of the PMOS transistor. The P-tub is created by a deep boron implant. A second boron implant is performed for punch-through suppressio...

In this work, we present detailed studies of two integration schemes for an aluminum-wire/tungsten-plug-based multilevel ultralarge scale integration ͑ULSI͒ interconnect module for subquartermicrometer complementary metal oxide semiconductor ͑CMOS͒ technologies, and discuss the benefits and drawbacks of each of them primarily from a process integration point of view. We demonstrate that an etch stop ͑ES͒ integration scheme in which the via etch stops on the TiN cladding layer could result in significantly improved via electromigration performance compared to an over etch ͑OE͒ integration scheme in which the via is overetched into the underlying Al͑Cu͒. We also identified several highly detrimental early failure modes associated with the OE structure, including contamination-induced stress void formation underneath the via, the metal extrusion inside the via, and the metal corrosion at the bottom of the via, and showed that such early failure modes could be prevented in the ES integration scheme. Even though there were some small penalties in the device performance in the ES integration scheme, the benefits in the reliability and the better tolerance to manufacturing process variation clearly justify the adoption of this robust multilevel ULSI interconnect module for subquartermicrometer CMOS technologies.In the past three decades, the interconnect technologies of integrated circuits ͑ICs͒ have undergone considerable evolution. 1 Due to increasing device density and chip functionality, the interconnect technology based on multilevel aluminum metal wires and tungsten plugs has become the dominant back-end-of-line technology in the semiconductor industry. Even though for some high-performance ICs such as microprocessors, the interconnect technology has gradually moved from Al to Cu to reduce the back end resistance capacitance ͑RC͒ delays, 2-5 IC chips based on Al wires/W plugs still account for the majority of chips that are currently produced worldwide. 6 Because of the heavy capital investments that have been made in and the good understandings that have been achieved by the Al wire/W plug technologies, this interconnect technology is expected to remain as the mainstream technology for the foreseeable future.The modern planar multilevel very large scale integrated ͑VLSI͒ interconnect technology is enabled by several important technological developments such as chemical mechanical polishing ͑CMP͒, 7 reactively sputtered TiN, 8 and chemical vapor deposition ͑CVD͒ W plug processes. 9 The dielectric CMP process provides a planar surface for the deposition of the subsequent interconnect layer, which prevents the propagation of the underlying topographies and defects and allows the building of a large number of levels of interconnects. The TiN is used as the cladding layer of Al metal, which greatly enhanced the resistance of Al wires to electromigration and stress migration. The TiN is also used as the barrier and adhesion layer for CVD W. 10 The CVD W plug process allows the filling of vias or contact windows with ve...

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