A Robust Multilevel Interconnect Module for Subquartermicrometer Complementary Metal Oxide Semiconductor Technology Integration

Abstract

In this work, we present detailed studies of two integration schemes for an aluminum-wire/tungsten-plug-based multilevel ultralarge scale integration ͑ULSI͒ interconnect module for subquartermicrometer complementary metal oxide semiconductor ͑CMOS͒ technologies, and discuss the benefits and drawbacks of each of them primarily from a process integration point of view. We demonstrate that an etch stop ͑ES͒ integration scheme in which the via etch stops on the TiN cladding layer could result in significantly improved via electromigration performance compared to an over etch ͑OE͒ integration scheme in which the via is overetched into the underlying Al͑Cu͒. We also identified several highly detrimental early failure modes associated with the OE structure, including contamination-induced stress void formation underneath the via, the metal extrusion inside the via, and the metal corrosion at the bottom of the via, and showed that such early failure modes could be prevented in the ES integration scheme. Even though there were some small penalties in the device performance in the ES integration scheme, the benefits in the reliability and the better tolerance to manufacturing process variation clearly justify the adoption of this robust multilevel ULSI interconnect module for subquartermicrometer CMOS technologies.In the past three decades, the interconnect technologies of integrated circuits ͑ICs͒ have undergone considerable evolution. 1 Due to increasing device density and chip functionality, the interconnect technology based on multilevel aluminum metal wires and tungsten plugs has become the dominant back-end-of-line technology in the semiconductor industry. Even though for some high-performance ICs such as microprocessors, the interconnect technology has gradually moved from Al to Cu to reduce the back end resistance capacitance ͑RC͒ delays, 2-5 IC chips based on Al wires/W plugs still account for the majority of chips that are currently produced worldwide. 6 Because of the heavy capital investments that have been made in and the good understandings that have been achieved by the Al wire/W plug technologies, this interconnect technology is expected to remain as the mainstream technology for the foreseeable future.The modern planar multilevel very large scale integrated ͑VLSI͒ interconnect technology is enabled by several important technological developments such as chemical mechanical polishing ͑CMP͒, 7 reactively sputtered TiN, 8 and chemical vapor deposition ͑CVD͒ W plug processes. 9 The dielectric CMP process provides a planar surface for the deposition of the subsequent interconnect layer, which prevents the propagation of the underlying topographies and defects and allows the building of a large number of levels of interconnects. The TiN is used as the cladding layer of Al metal, which greatly enhanced the resistance of Al wires to electromigration and stress migration. The TiN is also used as the barrier and adhesion layer for CVD W. 10 The CVD W plug process allows the filling of vias or contact windows with ve...