This paper proposes a new model for the partitioning and scheduling of a specification on partially dynamically reconfigurable hardware. Although this problem can be solved optimally only by tackling its subproblems jointly, the exceeding complexity of such a task leads to a decomposition into two phases. The partitioning phase is based on a new graph-theoretic approach, which aims to obtain near optimality even if performed independently from the subsequent phase. For the scheduling phase, a new integer linear programming formulation and a heuristic approach are developed. Both take into account configuration prefetching and module reuse. The experimental results show that the proposed method compares favorably with existing solutions

This paper considers the formulation of the variational model (VM) of autonomous circuits (oscillators) working in periodic steady-state conditions. The shooting method, which is largely used to compute the solution in the time domain when the VM is forced by a small-signal perturbation, is studied. The proposed analytical approach can be exploited to improve accuracy in the simulation of the effects of noise sources. In particular, we justify from an analytical standpoint the adoption of a suitable periodicity constraint in the shooting method. We exploit the properties of block circulant matrices that naturally arise in the description of the problem. We prove that the frequency of the small-signal perturbation must be different from that of the unperturbed oscillator to avoid inaccuracy of the shooting method due to the existence of singularities in the VM formulation, and derive a method that allows us to get closer to the singularity

SUMMARYIn this paper it is shown that a numerical method largely adopted for the simulation of noise in autonomous circuits is affected by singularities that manifest when the frequency at which the noise analysis is carried out approaches a harmonic of the autonomous circuit. The resulting noise power spectral density (PSD) is thus characterized by spurious spikes. The presence of these singularities is for the first time justified from an analytical standpoint and their effects are shown by simulating some oscillators, employed as benchmarks. Furthermore, the presented approach justifies the 1/( f s − f ) 2 shape of the PSD of noise at the output when the f s frequency approaches the f fundamental of a stable oscillator and the 1/| f s − f | 3 shape when the effects of flicker noise are manifest.

It is common nowadays to employ fpgas, not only as a means of rapidly prototyping and testing dedicated solutions, but also as a platform on which to implement actual production systems. The latter case comes in two flavors: Compile Time Reconfigurable systems, in which the configuration of the fpga is done once and is never changed, or Run Time Reconfigurable systems, where the configuration of the chip is modified during the execution [6].Although modern fpgas allow the designer to modify dynamically even only portions of the chip, to this date there is a lack of satisfying design methodologies that using only non-proprietary widely available tools make it possible to optimally implement a high-level specification into a partially dynamically reconfigurable system.The aim of this work is to propose a methodology for solving this problem. The main features of the Caronte methodology [1, 2] (which targets a board equipped with a Xilinx Virtex-ii Pro fpga with a Powerpc 405 processor) are: 1. full exploitation of partial dynamic reconfiguration; 2. the reconfiguration is internal (on the fpga a microprocessor handles the reconfiguration through the icap module -thus reducing the reconfiguration times; e.g. [4]); 3. a real-time unix-like operating system helps the management of complex systems with multiple tasks, and simplifies reconfiguration through an optimized device driver.The Hardware Architecture. Let us first describe the architecture of the solution resulting from the Caronte Methodology.In order to manage reconfiguration internally it is necessary to always have a processing element running on the chip that communicates with the icap port. This means that it will be necessary to have a part of the fpga which always remains the same during runtime (the fixed side, managing reconfiguration) while the rest of the available area is free for dynamic reconfiguration (the reconfigurable side).The reconfigurable side can at any instant be viewed as the collection of a certain number of independent functionalities which are mapped on the chip as need be. Hence the area of the reconfigurable part is divided in rectangular boxes, all sharing a minimal interface that allows them to interact with the rest of the system, such as the ibm CoreConnect bus. These boxes are called BlackBox es. Aside from that, each BlackBox has also a processing layer part which can be reconfigured to various tasks, always retaining the communication functionalities offered by the communication layer. The bus macro technology is used to establish unchanging routing channels between modules. From the implementation point of view, this means that each BlackBox is in fact an edk component made up of two vhdl, Verilog or edif files, the first one containing the architecturedependent logic interface and the second one the processing element hardware description.As for the fixed side is made up of six components: ICAP, used to read/write a configuration from/to the bram; IPCore Manager (ipcm), a layer between the kernel of the operating system t...

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