Field Programmable Gate Arrays (FPGAs) are in use to build high performance image processing systems . This paper presents the design and implementation of such an open FPGAbased Digital Camera System for image capturing and real-time image processing. Images captured with a CMOS sensor are initially stored in the system's memory and then they are displayed on an LCD Touch Panel. The main goal of this proposed architecture is to be used as a platform to implement and test advance image processing algorithms. Apart of thi s, the system supports the control of the image sensor, through the LCD Touch Panel. In addition, has the ability to communicate with a PC through a JTAG interface for storing the images on it. The structural element for th is proposed architecture was chosen to be the low cost and widely used at universities, Altera's DE2 development board.I. INTROD UCTIONThe constant reduction both of cost and size of image sensors and the increasing complexity of FPGA circuits let us to design and implement an FPGA-based Digital Camera System. Also, due to the appearance of the LCD Touch Panels this system could be able to be controlled from such a panel. Furthermore, the flexibility of FPGAs gives us the possibility to integrate additional applications and image processing algorithms to the system without any cost in hardware [1-3]. It's worth mentioning that the hardware image processing algorithms could be faster than the corresponding algorithms in CIC++.For the implementation of this system the development platform DE2 by Altera, the TRDB-D5M Camera and the TRDB-LTM LCD Touch Panel by Terasic have been chosen [5][6][7][8]. Some of the DE2's 1I0s have been used for the interconnection of the Camera and the LCD Touch Panel as well as for the communication between the DE2 and a Pc. Apart from the memories and the IIOs, the DE2 has a Cyclone II EP2C35 FPGA by Altera. This FPGA has 33216 logic elements , 483840 memory bits, 70 embedded multipliers and 4 Phase Locked Loops (PLL). The interfacing of all DE2's hardware components can be achieved through the FPGA. For the implementation of the system which is presented in block diagram in Fig.
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