This paper presents a BIST architecture, based on a single micro-programmable BIST Processor and a set of memory Wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing.
Multi-port memories are widely used as embedded cores in all communication System-on-Chip devices. Due to their high complexity and very low accessibility, Built-In Self-Test (BIST) is the most common solution implemented to test the different memories embedded in the system. This paper presents a programmable BIST architecture, based on a single microprogrammable BIST Processor and a set of memory Wrappers, designed to simplify the test of a system containing a large number of distributed multi-port memories of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing.
THE TELECOMMUNICATION systems marketincluding digital communication systems and real-time fragmented-data-structure applications such as asynchronous-transfer-mode (ATM) switches and video-related products-has grown significantly in the past few years. To compete in this market, industries must achieve high performance, robustness, availability, and reliability in their products, while keeping production costs as low as possible. To guarantee high performance and large data-processing capacities, system designers have integrated digital, analog, and radio-frequency devices. At the same time, strong reliability constraints have contributed to the evolution of highly reliable digital components.Memories are key components in telecommunication systems, playing a crucial role in system availability and serviceability. Memory components come in a wide variety of sizes, tech-Online and Offline BIST in IP-Core Design International Test Conference 92 This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines faultlatency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraints. RAM Address = = Offline BIST logic Address generator Background-pattern generator AG BGPG BIST controller = AG BGPG Addressing logic Comparator Comparators Figure 2. Concurrent online and offline BIST architecture.
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