A family of self-repair SRAM cores

Benso, Alfredo; Chiusano, Silvia; Natale, Giorgio Di; Prinetto, P.; Bodoni, M.L.

doi:10.1109/olt.2000.856639

Cited by 22 publications

(5 citation statements)

References 12 publications

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“…In [2], a row contains several cache lines and an individual cache line, rather than an entire row, can be replaced through modifications to the column multiplexers. Maintaining redundancy at a word level (e.g., 32-bit) allows more efficient utilization of redundant resources [5] [12]. Nevertheless, such fine-grain redundancy techniques are still inadequate for high defect densities.…”

Section: Defect Tolerance Techniquesmentioning

confidence: 99%

SEVA: A Soft-Error- and Variation-Aware Cache Architecture

Hung¹,

Goshima²,

Sakai³

2006

2006 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06)

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Section: Defect Tolerance Techniquesmentioning

confidence: 99%

SEVA: A Soft-Error- and Variation-Aware Cache Architecture

Hung¹,

Goshima²,

Sakai³

2006

2006 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06)

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“…Thus, they concentrate the large majority of manufacturing faults, affecting yield adversely. Hence, memory Built-In Self-Repair [1][2][3][4][5][6] is mandatory for maintaining acceptable fabrication yield. Moreover, field failures (soft-errors caused by neutrons and alpha particles, weak-cell faults activated during very-low voltage modes, circuit aging and wear-out) are a critical concern in memories.…”

Section: Introductionmentioning

confidence: 99%

An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAM

Papavramidou

Nicolaidis

Girard

2020

2020 IEEE 26th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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Memory system reliability is a serious concern in many systems today and is becoming more worrisome as technology scales, system size grows and the demand of aggressive voltage reduction becomes more stringent. Thus, disposing of memory repair architectures with strong fault tolerance capability at low cost is desirable. In this context, Error Correcting Codes (ECC)-based repair techniques were proposed and offer aggressive reduction of the repair cost for high defect densities. However, an important issue in advanced process nodes is the fact that, single particles induce Single-Event Upsets (SEUs) in neighbor memory cells, thus leading to Multi-Cell Upsets (MCUs) and Multi-Bit Upsets (MBUs), when they occur in the same memory word. In the case of memories, there exist efficient approaches mitigating this kind of MBUs, in particular the use of interleaving. But when a memory is repaired, the impact of MBUs on the circuitry repairing the faulty memory words should also be mitigated. This can be done by using a repair Content Addressable Memory (CAM) having interleaving at its data-words, or else an Offset CAM. In this paper we present and evaluate a novel repair approach that uses the Offset CAM in ECC-based Memory Repair and hence permits the mitigation of the MBUs affecting it.

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“…Also, faults in the spare parts are not considered. Subsequent works on word BISR [3] [4], [5] use the same basic scheme but improve various implementation aspects. These works too consider a low number of faults (e.g.…”

Section: Introductionmentioning

confidence: 99%