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Recently, several integrated radio receivers and transmitters operating at 60GHz have been developed in SiGe BiCMOS [1] and CMOS [2][3][4] technologies, by both industry and academia. As CMOS transistor gate lengths continue to scale downward, integration becomes possible at even higher frequencies. This paper presents a fully integrated receiver, with LNA, mixer, IF amplifier, fundamental-frequency quadrature VCO, and static frequency divider, operating at 95GHz in a 65nm general-purpose (GP) CMOS technology. The receiver consumes 206mW from a 1.2V/1.5V supply. With large RF and IF bandwidths of over 19GHz and 16GHz, respectively, it is suitable for passive-imaging applications, and for wireless chip-to-chip communication at data-rates exceeding 20Gb/s. Together with the recently reported 60GHz receiver in 90nm CMOS [4], this 95GHz receiver in 65nm CMOS demonstrates that scaling of entire mm-wave receivers is possible in both frequency coverage and across technology nodes, as predicted by Gordon Moore in the last paragraph of [5]. Furthermore, with the reduction of the die area occupied by lumped passives at higher frequencies, and with the intrinsic speed improvement anticipated in future CMOS technology nodes, one can expect that entire CMOS transceivers can be scaled to 120GHz in 45nm, and to 160GHz in 32nm technologies, and can be integrated with antennas and other systems as wireless I/Os for chip-to-chip communication at 40Gb/s. The architecture of the fabricated receiver is illustrated in Fig. 9.1.1. It uses an improved version of a shunt-series transformerfeedback 3-stage cascode LNA with a measured peak gain of 13dB and noise figure of 6 to 7dB [6]. The LNA is coupled to a doublebalanced Gilbert-cell mixer through transformer T1 which performs single-ended to differential conversion. The insertion loss of the transformer, measured on a separate test structure, is 1.7dB in the 57-to-94GHz range. A differential CML pair with 50Ω loads is used as the broadband IF amplifier. The LO signal is fed to the mixer using short transmission lines and transformer T2. A staticfrequency divider [7] is connected to the VCO to demonstrate the feasibility of a robust integrated 90GHz PLL. Due to space limitations, only one of the two divider outputs is made available for testing, and the other is terminated on-chip. A fundamental-frequency quadrature VCO, whose schematic is shown in Fig. 9.1.2, is used to generate the LO signals on-chip. The differentially tuned VCO is composed of 4 symmetrically coupled Colpitts oscillators. An RC filter is used in the VCO bias network to minimize the injection of supply noise, and thus prevent the degradation of the VCO phase noise. Four buffers, also shown in Fig. 9.1.2, are used to increase the output power of the VCO, and to differentially drive the mixer on one side, and the divider on the opposite side. Each of the VCO buffers is implemented as a single-stage common-source amplifier, which is matched to 50Ω at the output. A differential buffer topology with common-mode current so...