Anodic dissolution of n+‐, n‐, and n−‐type silicon in 5% aqueous hydrofluoric acid at moderate current densities results in the formation of etch channels which propagate in crystal‐oriented directions in the monocrystal. Density and depth of the channels are a function of the applied voltage, the donor concentration, and the exposure time of the electrolyte under anodic bias conditions. It is assumed that the channel formation originates at spots with a lower breakdown voltage of the depletion layer which exists on the surface of the crystal under reverse bias conditions. Channel formation in epitaxial n layers can occur during preferential electrochemical etching of the n+ substrate of n+n− structures. This is the case when the n+ to n− interface profile is not abrupt and when defects in the epitaxial layer are present. Some methods of restricting the influence of channels occurring during device processing are mentioned.

Preferential electrochemical etching of epitaxial structures has been applied to the fabrication of semiconductor devices. Preparation of thin layer devices and isolated structures is described. As an introduction to these applications, the etching of various epitaxial structures is described. Consideration is given to the manner in which the etching behavior is influenced by thermal treatment, the presence of diffusion areas, and crystal imperfections.Anodic dissolution of silicon in hydrofluoric acid has been described by several workers (1, 2). It was found by van Dijk (3) that electrochemical etching of epitaxially grown structures can be used to make thin silicon crystals. Using silicon slices of the n+n or the n+p type, the low-resistivity n + substrate can dissolve anodically and the etching process stops near the epitaxial boundary. Thin single crystals of silicon with a thickness down to 0.5# were prepared by van Dijk.This paper presents some applications of this electrochemical etching process to semiconductor technology. Before this is done, the etching behavior of homogeneously doped substrates and epitaxially grown structures will be considered in more detail. One application of the electrochemical etching process is the preparation of devices in thir~ silicon layers of high quality. These thin silicon layers can be advantageously used to make devices having improved performance. Similar devices may be made in thin silicon layers grown on sapphire, spinel, or other insulators. However, the crystal imperfections of these layers (often made by heteroepitaxial growing techniques), still limit the applications. Two new methods of preparing thin layer devices are described. In one method, lateral devices are fabricated in a thin silicon layer which is made on top of a polycrystalline silicon substrate with a SiO2 layer in between. In the second method of making thin layer devices, diffusions are carried out in the initial epitaxially grown structures, then the slice is etched, leaving a device with vertical junctions only.The electrochemical etching process can also be applied successfully in the preparation of isolated structures. A technique is presented for utilization of this process in the preparation of integrated circuits with dielectric isolation and beam lead air-gap isolation. Experimental ProcedureThe samples used consisted of homogeneously doped n-and p-type silicon slices and epitaxially grown slices with a highly doped substrate (~ 3.10 TM atoms/ cm 8) and an epitaxial layer with a dopant concentration lower than 2.1016 atoms/cm~. Both (111) and * Electrochemical Society Active Member.(100) oriented slices were used; slice diameters were between 32 and 40 ram.The homogeneously doped slices were chosen in the impurity concentration range from 1015 to 1019 atoms/ cm~. Prior to the electrochemical process, the slices were etched in HF (48%)-HNO3 (65%) (1: 10) etchant to remove work damage. Contact between the anode and the silicon was made by pressing a platinum strip (15 x 3 mm e) pressed agai...

Epitaxial silicon boride layers, located at the surface or within the bulk of single-crystal silicon, give rise to enhanced diffusion of B during annealing. A submonolayer buried boride layer releases ≈0.4 interstitials per B atom in the layer, generating a transient diffusion enhancement in the range of 10–100 for several minutes at 900 °C. The resulting profile broadening is comparable to that caused by ion implantation damage. At the same temperature, surface boride layers generate a diffusion enhancement of ∼6, part of which arises from the B diffusion flux and part from the chemical influence of the boride layer.

Leakage currents of n+-p-diodes, made on four different groups of p-type silicon substrates, are investigated at temperatures between 50 and 120'C. At these temperatures, diffusion of thermally generated minority carriers from the bulk is the dominant leakage current mechanism and determines the holding time of dynamic memories. Measurements at these temperatures show that for Czochralsky-grown wafers (CZ) with a high interstitial oxygen concentration as is used for intrinsic gettering, the leakage current densities are about 1OX higher than for CZ wafers with a low oxygen concentration or floating-zone wafers (FZ), and are about lOOx higher than for p-p +-epitaxial substrates. Simple analytical formulas explaining these large differences will be presented. Finally a short discussion about the optimum substrate for future high-density memories will be given.