No abstract
A 16Kb MEMORY with 770 logic gates for mainframe computers will be discussed. Latest computer systems adopt virtual storage and buffer storage systems to make programming easy as well as to improve cost performance. To realize these systems, a TLB (Table Lookaside Buffer) and a BAA (Buffer Address Array) are used as hardware t o implement storage control. For high density tables and increased speed performance, a logic-in-memory VLSI IA (Index Array)' has been developed. It integrates a 614413 memory and logic equivalent to 770 gates, and is used in the TLB and BAA for the storage control in the virtual storage system shown in Figure 1. The array speeds up the translation of virtual addresses into real ones and the control of BS (Buffer Storage), and consequently improves processor performance.The block diagram of the VLSI, shown in Figure 2 , consists of 16 sets of 64word x 6b memory cell array and circuits for compare, parity, input-output and control. ADR (Address) inputs select one from 64words and CA (Column Address) inputs select two from 16 sets. One of the circuits features is the function of comparing 6b readout data from the stored memory cells with 6b CDIs (Compare Data Inputs). A low voltage level signal appears at the CDO (Compare Data Output) when CDIs coincide with readout data. Furthermore, a FS (Full Select) input is designed t o strengthen the comparing function. When FS is high, 16 sets can be compared simultaneously. As a result, compareexecution time is lessened t o one eighth. It is extremely useful for TLB and BAA application.The memory cell circuit is a conventional parallel diode cell., A SBD (Schottky Barrier Diode) is used as a clamp diode to realize fast read/write performance. In other logic circuits, ECL (Emitter Coupled Logic) is used.Address access time and compare access time are 6. 711s and 3.5ns, respectively. Power dissipation is 5.2W.The LSI integrates 57,000 elements on the chip. To obtain this integration, advanced bipolar process technologies are employed. The basic process is oxide isolation with double layer metalization. The line width plus spacing of first and second metals is 6 p m and 12pm, respectively. Major electrical performance and features are tabulated in Table 1. Process features are: 2/nn anisotropic groove which realizes a high packing density, boron and arsenic implantation to result in shallow base and emitter junctions, SBD with a platinum-silicide contact, phosphorus implantation which helps to control the forward voltage of SBD, dry etching of first and second metals and insulators between them.high cutoff frequency and a low base resistance; fT = 4GHz,, rbb = 300a. Device parameters are summarized in Table 2.the chip are shown in Figure 3 and Figure 4, respectively.
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