An all O.5pm CMOS transceiver IC is capable ofsupporting 768kb/s rates on a single cooper loop. Trade-offs between data rate and loop length are afforded by support of multiple bit rates. The same transmitter concept is also integrated for asymmetric digital subscriber line (ADSL), and tested for downstream rates of 6000-8000kb/s. (External line driver for ADSL).The transceiver covers the full set ofANSI T1.601 Basic Rate ISDN (U-interface) loops while providing 2.5 times the throughput of existing U-interface transceivers. Nearly 5 times the throughput (768kbIs) is achieved even in the presence of worst-case selfcrosstalk. The additional performance is achieved by combination of coding, digital, and analog techniques. The data pump uses multiple constellation sizes and symbol rates to optimize the system for various combinations of reach and data rate while maintaining spectral compatibility. The system achieves decision feedback equalizer (DFE) levels of performance plus coding gain through the use of Tomlinson-Harashima pre-coding and trellis coding. Figure 14.4.1 and Figure 14.4.2 show the block diagrams of the digital and analog portions.On the transmit side, baud-rate transmit data is oversampled, then noise-shaped with a secondorder highpass noise-shaping (NS) of ( l -~-l )~ on the truncated signals. 15b digital codes are reduced to 6 bit + sign, entering the DAC. It is a fast multi bit non-calibrated DAC with speed up to l.lMHz, a t 14b accuracy. The DAC is followed by a third-order lowpass filter (LPF) to attenuate out-of-band noise. Two nestedMiller-compensated, class-AB amplifiers with multiple differential stages, a t the first and second gain stages for both positive and negative drive provide 4V peak-to-peak swing on 5V/5% rails, which leads to lower equivalent current (15% ), into the two 10R load resistors. Simulation indicates harmonic distortion below 93dB for 4V/llOmA peak voltage.On the receive side, a n automatic gain control (AGC) having 24dB range is adjusted to make the best use of the dynamic range of the 2-1 MASH ZA-ADC. The ADC runs a t a 20.48MHz sampling rate, and provides 13b. The decimator down-samples the ADC output to the baud rate, where it passes through a n adaptive linear equalizer, is Viterbi (trellis), Tomlinson decoded, and unscrambled. The third block is the analog echo canceller hybrid. It is software programmable to all ISDN loops including bridged taps. Figure 14.4.3 shows the transceiver bias section. Multiple resistor types are used. To save area, high ohmic resistors are used with M2 and opl to set the converters amplitude levels, (over-load point). Low ohmic resistors (RI, R2, M1) set the amplifiers and line driver currents. Low ohmic resistors have temperature and process variations 30% lower than high ohmic resistors, reducing chip-to-chip power variations. The line drivers use 7000pn/0.5pm devices. Minimum channel length devices causes large Gds variations and in return part-to-part idle current variations. To reduce this further, two trimming bits are used (Rl,R...
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