A 700/900mW/channel CMOS dual analog front-end IC for VDSL with integrated 11.5/14.5dBm line drivers

Moyal, M.; Groepl, M.; Werker, H.; Mitteregger, G.; Schambacher, J.

doi:10.1109/isscc.2003.1234364

Cited by 26 publications

(15 citation statements)

References 3 publications

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“…1). Moreover, the continuous time implementation of ADCs extends the input frequency range from a few 100 kHz up to a few 10 MHz and proves to be very power efficient [10,14,18].…”

Section: Introductionmentioning

confidence: 99%

A 22 mW 512 MHz CMOS continuous time sigma delta ADC in 1.2 V with 16 MHz signal bandwidth and 70 dB dynamic range

Yuan

Yang

2012

Analog Integr Circ Sig Process

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A wide bandwidth continuous time sigma delta analog-to-digital conversion is implemented in 130 nm process. The circuit is targeted for wide bandwidth applications such as video or wireless base-stations. The thirdorder continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency. To reduce the clock jitter sensitivity, nonreturn-tozero DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer, and the degradation of modulator stability due to excess loop delay is avoided with this architecture. The sigma delta ADC achieves a 60 dB SNR and a 59.3 dB signal-to-noise-plusdistortion ratio over a 16 MHz signal band at an oversampling ratio of 16. The power consumption of the continuous time sigma delta modulator is 22 mW from the 1.2 V supply.

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“…1). Moreover, the continuous time implementation of ADCs extends the input frequency range from a few 100 kHz up to a few 10 MHz and proves to be very power efficient [10,14,18].…”

Section: Introductionmentioning

confidence: 99%

A 22 mW 512 MHz CMOS continuous time sigma delta ADC in 1.2 V with 16 MHz signal bandwidth and 70 dB dynamic range

Yuan

Yang

2012

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…The open-loop configuration is also characterized by a poor linearity in the voltage to current conversion, whereas the closed-loop one can have a highly linear voltage-to-voltage transfer function. Since the new OFDM-based communication standards require high linearity for any circuit in the signal path, in order to minimize the intermodulation among the multiple carriers, new highly linear OTAs are required in order to meet the linearity and bandwidth requirements [3][4][5]. The use of open-loop OTAs also avoid the excessive power consumption required by typical high-bandwidth amplifiers with global feedback.…”

Section: Introductionmentioning

confidence: 99%

A tunable highly linear CMOS transconductor with 80 dB of SFDR

et al. 2009

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“…Recently, the popularity of continuous-time ADCs has been growing for application-specific ICs [2]- [4]. Moreover, continuous-time implementation of ADCs extends the input frequency range from a few 100 kHz up to a few 10 MHz and proves to be very power efficient [5]- [7].…”

Section: Introductionmentioning

confidence: 99%

A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

Mitteregger

Ebner

Mechnig

et al. 2006

IEEE J. Solid-State Circuits

270

125

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A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time 61 modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time 61 ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The 61 ADC achieves 76-dB SNR, 78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT 61 modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply.

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A 700/900mW/channel CMOS dual analog front-end IC for VDSL with integrated 11.5/14.5dBm line drivers

Cited by 26 publications

References 3 publications

A 22 mW 512 MHz CMOS continuous time sigma delta ADC in 1.2 V with 16 MHz signal bandwidth and 70 dB dynamic range

A 22 mW 512 MHz CMOS continuous time sigma delta ADC in 1.2 V with 16 MHz signal bandwidth and 70 dB dynamic range

A tunable highly linear CMOS transconductor with 80 dB of SFDR

A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

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