A prototype of a 34 x 34 pixel image sensor, implementing real-time analog image processing, is presented. Edge detection, motion detection, image amplification, and dynamic-range boosting are executed at pixel level by means of a highly interconnected pixel architecture based on the absolute value of the difference among neighbor pixels. The analog operations are performed over a kernel of 3 x 3 pixels. The square pixel, consisting of 30 transistors, has a pitch of 35 microm with a fill-factor of 20%. The chip was fabricated in a 0.35 microm CMOS technology, and its power consumption is 6 mW with 3.3 V power supply. The device was fully characterized and achieves a dynamic range of 50 dB with a light power density of 150 nW/mm2 and a frame rate of 30 frame/s. The measured fixed pattern noise corresponds to 1.1% of the saturation level. The sensor's dynamic range can be extended up to 96 dB using the double-sampling technique.
This paper presents the design principles underlying the video nodes of long-lifetime wireless networks. The hardware and firmware architectures of the system are described in detail, along with the system-power-consumption model. A prototype is introduced to validate the proposed approach. The system mounts a Flash-based field-programmable gate array and a highdynamic-range complementary metal-oxide-semiconductor custom vision sensor. Accurate power measurements show that the overall consumption is 4.2 mW at 3.3 V in the worst case, thus achieving an improvement of two orders of magnitude with respect to video nodes for similar applications recently proposed in the literature. Powered with a 2200-mAh 3.3-V battery, the system will exhibit a typical lifetime of about three months. Index Terms-Complementary metal-oxide-semiconductor (CMOS) vision sensor, field-programmable gate array (FPGA), image processing, people counter, surveillance, ultralow-power node, wireless camera network (WCN).
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