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Non Volatile Memories (NVMs) can undergo different types of disturbances. These disturbances are particular to the technology and the cell structure of the memory element. In this papel; we develop a coupling fault model that appropriately models disturbances in Flash memories that use floating gate transistor as their core memory element. We describe the behavior of faulty cells under different fault models and how their characteristics change under each model. We demonstrate the inappropriateness of conventional march algorithms for testing flash memories and present a procedure to derive Pseudo-algorithms that can be used in testing flash memories. In addition we present an eficient test that detects these disturbances under diflerent fault models developed in this papel:

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Flash memories can undergo three di erent types of disturbances, DC-Programming, DC-Erasure, and Drain Disturbance. These faults are s p eci c to ash memories and do not occur in RAMs. In this paper, we discuss these disturbances, their causes, and develop fault models that capture the characteristics of these faults. We present optimal and near optimal algorithms to detect these faults in ash memories.

Chalcogenide based Phase Change Memory (PCM) is a promising type of non-volatile memory that will possibly replace the currently wide spread flash memory. Current research on PCMs targets the integration, feasibility, and reliability of such memory technology into the widely used CMOS process technology. Such studies identified special failure modes, known as disturbs, that could occur in PCMs. In this paper, we identify these failures and analyze their defective behaviors. Moreover, we develop fault models for such disturbs in addition to faults caused by opens and shorts in the core memory cell. Further, we propose an efficient test algorithm, called March-PC, to detect all faults discussed in this work.