Nanoscale control of doping profiles in semiconductor devices is becoming of critical importance as channel length and pitch in metal oxide semiconductor field effect transistors (MOSFETs) continue to shrink toward a few nanometers. Scanning tunneling microscope (STM) directed self-assembly of dopants is currently the only proven method for fabricating atomically precise electronic devices in silicon. To date this technology has realized individual components of a complete device with a major obstacle being the ability to electrically gate devices. Here we demonstrate a fully functional multiterminal quantum dot device with integrated donor based in-plane gates epitaxially assembled on a single atomic plane of a silicon (001) surface. We show that such in-plane regions of highly doped silicon can be used to gate nanostructures resulting in highly stable Coulomb blockade (CB) oscillations in a donor-based quantum dot. In particular, we compare the use of these all epitaxial in-plane gates with conventional surface gates and find superior stability of the former. These results show that in the absence of the randomizing influences of interface and surface defects the electronic stability of dots in silicon can be comparable or better than that of quantum dots defined in other material systems. We anticipate our experiments will open the door for controlled scaling of silicon devices toward the single donor limit.
We have fabricated a nanoscale ring of phosphorus dopants in silicon using a scanning tunneling microscope to pattern a hydrogen resist layer. Low-temperature magnetotransport measurements reveal both aperiodic universal conductance fluctuations and periodic Aharonov–Bohm oscillations. From the ratio of the h/e and h/2e components of the Aharonov–Bohm oscillations, we estimate a phase coherence length of ≃100 nm at a temperature T=100 mK. This is in agreement with previous results from weak localization measurements on low-dimensional dopant devices in silicon.
An important driving force behind the microelectronics industry is the ability to pack ever more features onto a silicon chip, by continually miniaturising the individual components. However, after 2015 there is no known technological route to reduce devices below 10nm. We demonstrate a complete fabrication strategy towards atomic-scale device fabrication in silicon using phosphorus as a dopant in combination with scanning probe lithography and high purity, low temperature crystal growth. A major advantage of this strategy is the ability to investigate the role of dopant placement and atomically controlled growth on electronic device operation.
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