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This paper presents a template matching technique for detecting defects in VLSI wafer images. This method is based on traditional techniques of image analysis and image registration, but it combines the prior art of image wafer inspection in a new way, using prior knowledge like the design layout of VLSI wafer manufacturing process. This technique requires a golden template of the patterned wafer image under inspection which is obtained from the wafer image itself mixed to the layout design schemes. First a mapping between physical space and pixel space is needed. Then a template matching is applied for a more accurate alignment between wafer device and template. Finally, a segmented comparison is used for finding out possible defects. Results of the proposed method are presented in terms of visual quality of defect detection, any misalignment at topology level and number of correctly detected defective devices.