With the advent of the big data era, applications are more data-centric and energy efficiency issues caused by frequent data interactions, due to the physical separation of memory and computing, will become increasingly severe. Emerging technologies have been proposed to perform analog computing with memory to address the dilemma. Ferroelectric memory has become a promising technology due to field-driven fast switching and non-destructive readout, but endurance and miniaturization are limited. Here, we demonstrate the α-In2Se3 ferroelectric semiconductor channel device that integrates non-volatile memory and neural computation functions. Remarkable performance includes ultra-fast write speed of 40 ns, improved endurance through the internal electric field, flexible adjustment of neural plasticity, ultra-low energy consumption of 234/40 fJ per event for excitation/inhibition, and thermally modulated 94.74% high-precision iris recognition classification simulation. This prototypical demonstration lays the foundation for an integrated memory computing system with high density and energy efficiency.

Synaptic devices are necessary to meet the growing demand for the smarter and more efficient system. In this work, the anisotropic rhenium disulfide (ReS 2) is used as a channel material to construct a synaptic device and successfully emulate the long-term potentiation/depression behavior. To demonstrate that our device can be used in a large-scale neural network system, 165 pictures from Yale Face database are selected for evaluation, of which 120 pictures are used for artificial neural network (ANN) training, and the remaining 45 pictures are used for ANN testing. A three-layer ANN containing more than 10 5 weights is proposed for the face recognition task. Also 120 continuous modulated conductance states are selected to replace weights in our well-trained ANN. The results show that an excellent recognition rate of 100% is achieved with only 120 conductance states, which proves a high potential of our device in the artificial neural network field.

Vertical-nanowire-FETs (VNW-FETs) get a lot of attentions as promising devices in sub-5 nm nodes. Moreover negative capacitance (NC) is an emerging technique that can break through the lower limit of sub-threshold swings (SS) to reduce the power consumption of MOSFETs. However, suffering from the limitation of short gate length there is lack of controllable and integrative structures for high performance VNW-FETs with NC (NC VNW-FETs). In this study, a useful structure is proposed for NC VNW-FET, which can be used in high density ICs, and suitable for capacitance matching. To examine their performance, NC VNW-FETs were simulated by TCAD coupled with Landau-Khalatnikov ferroelectric equation of which the ferroelectric parameters were calibrated from our experimental HfZrO data. It's found that, for a certain ferroelectric layer thickness, when the NC area is larger than a critical area which is related to the Hf/Zr ratios and the thickness of ferroelectric layers, NC VNW-FET performance increases with the decreasing of NC area. Oppositely the NC VNW-FET is unstable when the NC area is smaller than the critical area. With the area optimized 9 nm Hf0.5Zr0.5O2 film, the Ion/Ioff ratio increases to 6 orders of magnitude and the minimum SS has reduced to 29.84 mV/decade.