Simulations of VNW-FETs with Adjustable Spacer-Like Negative Capacitors Based on Experimental Data

Abstract

Vertical-nanowire-FETs (VNW-FETs) get a lot of attentions as promising devices in sub-5 nm nodes. Moreover negative capacitance (NC) is an emerging technique that can break through the lower limit of sub-threshold swings (SS) to reduce the power consumption of MOSFETs. However, suffering from the limitation of short gate length there is lack of controllable and integrative structures for high performance VNW-FETs with NC (NC VNW-FETs). In this study, a useful structure is proposed for NC VNW-FET, which can be used in high density ICs, and suitable for capacitance matching. To examine their performance, NC VNW-FETs were simulated by TCAD coupled with Landau-Khalatnikov ferroelectric equation of which the ferroelectric parameters were calibrated from our experimental HfZrO data. It's found that, for a certain ferroelectric layer thickness, when the NC area is larger than a critical area which is related to the Hf/Zr ratios and the thickness of ferroelectric layers, NC VNW-FET performance increases with the decreasing of NC area. Oppositely the NC VNW-FET is unstable when the NC area is smaller than the critical area. With the area optimized 9 nm Hf0.5Zr0.5O2 film, the Ion/Ioff ratio increases to 6 orders of magnitude and the minimum SS has reduced to 29.84 mV/decade.

Investigation of Negative DIBL Effect and Miller Effect for Negative Capacitance Nanowire Field-Effect-Transistors

“…ECENTLY, to develop advanced CMOS technology in the sub-3-nm node range, negative capacitance field-effect-transistors (NCFETs) have attracted more attention owing to their exceptional performance and excellent process compatibility with existing CMOS technology [1]- [5]. Actually, nanowire field-effect-transistors with negative capacitance (NC) (NC NWFETs) have been considered the most promising candidates for sub-3-nm node [6]- [7]. Due to the enormous complexity of NC NWFETs, it is quite important to investigate the unconventional effects of NC NWFETs.…”

Investigation of ferroelectric field-effect transistors using a replacement metal gate process

“…For example, a higher E C and lower P r increase the value of α in equation ( 2) which results in a greater amplification of the surface potential which in turn yields a higher current, lower SS, and larger hysteresis window. Partial research has been done by TCAD simulation in our previous work [21] and Peng's work [27]. Further experimental verification is needed in the future.…”

“…Consequently, NCFETs can break through the lowest limit of the SS to lower the supply voltage and overall power consumption, which has been investigated theoretically [10][11][12][13][14][15] and confirmed by experiments [16][17][18][19][20]. Owing to their exceptional performance and excellent process compatibility with existing CMOS technology, NCFETs have attracted a great deal of attention from both science and technology communities and have been considered the most promising candidates for sub 3 nm technology nodes [21][22][23]. In a 45 nm technology node, to suppress the short-channel effect, a high-κ metal gate was introduced and a replacement metal gate process was used because high-κ materials, such as HfO 2 , are not resistant to hightemperature processes.…”

Investigation of device-circuit for negative capacitance vertical nanowire FETs based on SPICE model

“…The transient characteristics of NC VNW-FETs with different A FE (A FE = 0 nm 2 represents for conventional VNW-FET) are shown in figure 3. It is evident that as A FE decreases, switching characteristics become steeper due to the amplification in V int provided by NC [22,23]. However, the NC VNW-FET is unstable when A FE is smaller than a certain critical area.…”