This article introduces a robust and computationally efficient technique for the design of fluctuation-resistant structures (fault-tolerant) semiconductor devices. This technique can be applied to the computation of the doping profiles that minimize the intrinsic variations in various parameters induced by random dopant fluctuations. The technique is based on the evaluation of doping sensitivity functions, which are defined as elements of the space adjoint to the space of square integrable functions generated by all possible doping variations. The optimized doping profiles are computed by minimizing the standard deviation of fluctuations of different parameters, and constraints are taken into consideration by using the Lagrange multiplier method. The technique introduced here can be applied to any semiconductor device, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), silicon-on-insulator (SOI) devices, and fin field-effect transistors, and can be used in the framework of any transport model. The technique is applied to the minimization of the random dopant-induced fluctuations of threshold voltages in 25 nm channel length MOSFETs and double-gate fully depleted SOI devices. It is shown that, by carefully designing the doping profiles, random dopant-induced fluctuations can be suppressed between 16% in the case of constrained optimization and 35% in the case of unconstrained optimization for devices with channel lengths smaller than 25 nm. Analytical equations are derived for the optimum doping profiles that minimize the effects of random dopant fluctuations on the threshold voltage in MOSFETs. It is shown that, in both long-channel and short-channel devices, the size of the undoped region should be at least 14 of the width of the depletion region in order to suppress efficiently the random dopant-induced fluctuations.
Traditional algorithms for simulating quantum computers on classical ones require an exponentially large amount of memory, and so typically cannot simulate general quantum circuits with more than about 30 or so qubits on a typical PC-scale platform with only a few gigabytes of main memory. However, more memory-efficient simulations are possible, requiring only polynomial or even linear space in the size of the quantum circuit being simulated. In this paper, we describe one such technique, which was recently implemented at FSU in the form of a C++ program called SEQCSIM, which we releasing publicly. We also discuss the potential benefits of this simulation in quantum computing research and education, and outline some possible directions for further progress.
An automated technique is presented for the computation of the doping profiles that minimize the intrinsic fluctuations of various parameters induced by random doping fluctuations in semiconductor devices. The technique is based on the computation of the doping sensitivity functions of the parameters under consideration and the constrained minimization of the standard deviation of fluctuations by using the Lagrange multipliers technique. The technique is then applied to the minimization of the random doping induced fluctuations of the threshold voltage in 40-nm channel length MOSFET device.
Conventional vector-based simulators for quantum computers are quite limited in the size of the quantum circuits they can handle, due to the worst-case exponential growth of even sparse representations of the full quantum state vector as a function of the number of quantum operations applied. However, this exponential-space requirement can be avoided by using general space-time tradeoffs long known to complexity theorists, which can be appropriately optimized for this particular problem in a way that also illustrates some interesting reformulations of quantum mechanics. In this paper, we describe the design and empirical space/time complexity measurements of a working software prototype of a quantum computer simulator that avoids excessive space requirements. Due to its space-efficiency, this design is well-suited to embedding in single-chip environments, permitting especially fast execution that avoids access latencies to main memory. We plan to prototype our design on a standard FPGA development board.
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