For mixed-signal systems, identifying the analog and digital circuit blocks in the transistor-level netlist has many benefits for system analysis and verification. However, existing approaches still have difficulty handling large mixed-signal designs with millions of transistors, especially when multiple analog structure patterns are included. In this paper, we propose an efficient structure recognition methodology to support analyzing highly complex designs with various circuit structures and different devices. In order to tackle the complexity of real cases, a hierarchical partition-based analysis methodology and an encoding-based fast screening technique are proposed in this work. To correctly ascertain the boundary of analog and digital structures, we propose an enhanced direct current connection (DCC) partition method and combine it with the analog structure analysis flow. The non-transistor devices, such as resistors and capacitors, are also included in our recognition flow to improve the recognition capability and accuracy. As demonstrated with two industrial cases, the behavioral models generated from the structure recognition results do help to improve the efficiency of the AMS system verification.
Low-power analog design is a hot topic for various power efficient applications. Sizing low-power analog circuits is not easy because the increasing uncertainties from low-voltage techniques magnify process variation effects on the design yield. Simulation-based approaches are often adopted for analog circuit sizing because of its high accuracy and adaptability in different cases. However, if process variation is also considered, the huge number of simulations becomes almost infeasible for large circuits. Although there are some recent works that adopt machine learning (ML) techniques to speed up the optimization process, the process variation effects are still hard to be considered in those approaches. Using the popular evolutionary algorithm (EA) as an example, this paper proposes an ML-assisted prediction model to speed up the variation-aware circuit sizing technique for low-voltage analog circuits. By predicting the likelihood for a design that has worse performance, the enhanced EA process is able to skip many unnecessary simulations to reduce the convergence time. Moreover, a novel force-directed model is proposed to guide the optimization toward better yield. Based on the performance of prior circuit samples in the EA optimization, the proposed force model is able to predict the likelihood of a design that has better yield without time-consuming Monte Carlo simulations. Compared with prior works, the proposed approach significantly reduces the number of simulations in the yield-aware EA optimization, which helps to generate practical low-voltage designs with high reliability and low cost.
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