An MOS transistor fabricated on (001) β-Ga 2 O 3 exfoliated from a commercial (−201) β-Ga 2 O 3 substrate is reported. A maximum drain current of 11.1 mA/mm was measured, and a non-destructive breakdown was reached around 80 V in the off state. Threshold voltage of +2.9 V was extracted at 0.1 V drain bias, and peak transconductance of 0.18 mS/mm was measured at V DS = 1 V, corresponding to a field effect mobility of 0.17 cm 2 /Vs. Hall effect and electron spin resonance data suggested that electron conductivity was due primarily to O vacancy donors (V O + ) with an estimated density of 2. The single-crystal monoclinic (β) phase of Ga 2 O 3 is an advantageous material for high-power, high-temperature electronic device applications due to its high energy gap (4.8-4.9 eV) and high breakdown field (8 MV/cm), yielding a nearly ten-fold higher Baliga figure of merit than that of 4H-SiC (BFOM Ga 2 O 3 = 3444, BFOM 4H-SiC = 300).1 Commercially available β-Ga 2 O 3 substrates enable the epitaxial growth of low defect density epitaxial β-Ga 2 O 3 by a number of methods, including chemical vapor deposition, hydride vapor phase epitaxy (HVPE), and molecular beam epitaxy (MBE), among others.2-6 Schottky barrier diodes (SBDs) based on Ga 2 O 3 have exhibited very low turn on voltage and reverse leakage current, suggesting that unintentionally doped Ga 2 O 3 has extremely low generation/recombination rates and thus a high photoconductive gain.7 Advances in doping control have enabled exceptional early reports of metal-and metal-insulatorgated field effect transistors (MOSFETs). Wong et al. demonstrated a field-plated β-Ga 2 O 3 MOSFET with a breakdown voltage of over 750 V using a Si-implanted channel.8 Most recently, Green and coworkers have reported a Ga 2 O 3 MOSFET with a Sn-doped channel and a 0.6 μm gate-drain spacing to operate at 200 V drain bias, experimentally demonstrating gate-drain fields in excess of 3 MV/cm. 9This excellent progress has positioned Ga 2 O 3 as a viable candidate for next generation material for power applications. However, no demonstration of normally-off operation, a key requirement for fail-safe operation of power switches, has been achieved or proposed to-date.From a practical perspective, development of Ga 2 O 3 transistors has been limited by the availability of device-quality epitaxial films. For this reason, early reports have exploited the relatively large a-plane lattice constant of β-Ga 2 O 3 (1.2 nm) in order to mechanically exfoliate thin films from the (001) plane of a substrate using the scotch tape method to fabricate back-gated devices. 10,11 We employed a similar method to transfer a thin (∼300 nm) Ga 2 O 3 flake onto a SiO 2 /Si substrate, 12 and performed a standard top-side insulated-gate process to fabricate a three-terminal device. We also utilized a high-k HfO 2 gate dielectric process, as only SiO 2 and Al 2 O 3 have been reported to-date. 13,14Experimental A thin sliver of Ga 2 O 3 was cleaved along the (001) face of an on-axis (−201), non-intentionally n-type doped (∼3 ×...

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In this report, we study the effectiveness of hydrogen plasma surface treatments for improving the electrical properties of GaSb/Al2O3 interfaces. Prior to atomic layer deposition of an Al2O3 dielectric, p-GaSb surfaces were exposed to hydrogen plasmas in situ, with varying plasma powers, exposure times, and substrate temperatures. Good electrical interfaces, as indicated by capacitance-voltage measurements, were obtained using higher plasma powers, longer exposure times, and increasing substrate temperatures up to 250 °C. X-ray photoelectron spectroscopy reveals that the most effective treatments result in decreased SbOx, decreased Sb, and increased GaOx content at the interface. This in situ hydrogen plasma surface preparation improves the semiconductor/insulator electrical interface without the use of wet chemical pretreatments and is a promising approach for enhancing the performance of Sb-based devices.

Surface morphologies associated with thermal desorption: Scanning tunneling microscopy studies of Br-GaAs (110) We have studied single-walled carbon nanotubes ͑SWNTs͒ on the cleaved GaAs͑110͒ surface using an ultrahigh vacuum ͑UHV͒ scanning tunneling microscope ͑STM͒. SWNTs were deposited via an in situ UHV dry contact transfer ͑DCT͒ procedure and subsequent STM images provide simultaneous resolution of the nanotube chirality and substrate lattice. Room temperature scanning tunneling spectroscopy measurements reveal semiconducting nanotube features within the substrate band gap indicative of a transport mechanism other than direct tip to substrate tunneling. Nanotube gaps scale appropriately and are found to be in reasonable agreement with theoretical values. SWNTs were transferred to the GaAs surface with minimal additional contamination and no indication of damage to either nanotube or substrate, recommending the DCT technique as a general deposition procedure for a variety of systems incompatible with ambient processing.

Naturally occurring carbon‐nanotube heterojunctions provide a unique opportunity for studying nearly one‐dimensional metal–semiconductor (M–S) interfaces. Coupling the nanoscale lateral precision of the ultrahigh‐vacuum STM with spatially‐resolved electronic measurements enables detailed characterization of a single‐walled carbon nanotube M–S junction (see figure) and of the metal‐induced gap states present at the interface.