Amongst solutions to connect the die to the package, thermosonic wire bonding process remains widely used. However, the introduction of low-k dielectric materials, and the feature size decrease of IC chips to follow Moore's law, pose great integration challenge.This paper aims to demonstrate the compliance of the proposed modeling approach with the aids of experimental validations. 3D multi scale simulation of both bonding process and wire pull test is carried out. Using a previously validated homogenization procedure to include pad structure description even at the global scale, stress fields acting in the copper/low-k stack are evaluated. The modeling strategy also includes an in-house developed energy based analysis.For the experimental part, a wide range of wire bond trials have been performed in order to qualify the 65-nm technology node. On behalf of that, several bond pad architectures have been implemented and wire bonded on a test vehicle. It was found a significant effect of the copper/low-k design on peeling failure rates, in particular with severe bonding conditions. In this paper, typical modeling results are presented. Contrary to stress based one, the energy based analysis shows a better ability to forecast the observed failed interface. From simulation results obtained, it is confirmed that the bonding process plays major role in the peeling failure, despite the fact that most of them are observed during the wire pull test. Failure mechanisms are also proposed. Then, the implemented pad structures are evaluated and analyzed. Both general trends and architecture ranking are provided. Simulations are then faced to experimental results and a full agreement is found. The complementary nature of the energy based failure criteria is again highlighted through a clearer discrimination of the tested structures.Finally, the simulation procedure with confirmed experimental results demonstrates its ability in design and process optimizations by providing a better understanding of pad peeling failure mechanisms.
Blade sawing has been widely used in semiconductor industry and it is the most conventional process in semiconductor manufacturing to produce singulated ICs. This well established dicing technique poses challenges to process next generation of wafer when the wafer fabrication technology is fast scaling down in node size to 90-, 45-, 32and 22-nm where low-k dielectric is used. ILD (Inter-Layer Dielectric) and metal layers peelings, cracks, chipping, and delamination are the most common dicing defects observed on low-k wafer processed by the traditional blade sawing techniques. This paper presents an experimental study to improve the dicing performance and quality on processing low-k wafer by using a combination of laser grooving process and traditional blade sawing technique. Some low-k wafers were used as test vehicles. The laser process outcomes and responses are governed by the changes of process input parameters such as laser power, repetition rate, grooving feed speed, defocus amount and street index. The effects of the process parameters on the laser kerf geometry, grooving edge quality and defects are evaluated by using optical microscopy and scanning electron microscopy (SEM). Experimental results have shown that the dicing quality produced by using a combination of laser grooving and blade sawing technique can significantly minimize the dicing defects. It is one of the potential solutions to address the quality and yield issues in low-k wafer dicing. The key challenges of laser grooving and recommended future development works are discussed.
In the past, mechanical sawing of low-k devices always poise to be a big challenge to achieve good dicing quality. This is because of the weak mechanical properties of low-k dielectric material used. Moving forward, this challenge will be even greater with the introduction of ultra low-k dielectric material in 45nm and 32nm wafer node size. An alternative dicing process such as laser grooving is gaining popularity in resolving the low-k saw problems. This paper discusses the development works of laser grooving and the following saw process of CMOS 90nm and 45nm devices, both in flip chip and wire bond packages. The discussion also includes wafer surface contamination prevention, laser process parameters selection, Heat Affected Zone (HAZ) analysis and laser process defects. A series of package reliability stress was carried out to prove the robustness of the finalized process parameters and conditions.
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