In this paper, we present the effect of plasma descum by O 2 /C 2 F 6 gas mixture on the via formation of photosensitive BCB layer and compare it with that of RF cleaning. Test vehicle was fabricated on Si wafer with Cu/photosensitive BCB layer structure and ECR-CVD system was used to descum the via. Residues at via bottom after the descum process were investigated by AES (auger electron microscope) and SEM (scanning electron microscope). It is shown in this work that O 2 /C 2 F 6 plasma etching and the RF cleaning are effective for organic C, native C respectively, therefore the via descum by a combination of plasma etching with O 2 /C 2 F 6 gas mixture and RF cleaning can efficiently remove the via residues
This study investigated how the shapes of high density electroplated bump and reflowed bumps depend on via size.The solder bump was fabricated by subsequent processes as follows. After sputtering a Ti/Cu seed layer on a 5-inch Siwafer, a thick photoresist for via formation was obtained by multi-coating, and vias with various diameters were defined by a conventional photolithography technique using a contact alinger with an I-line source. After via formation, eutectic solder bumps were electroplated. After reflow, the reflowed bump diameters at the bottom were unchanged compared with the electroplated diameters. The electroplated bump and reflowed bump shapes, however, depended significantly on the via size. The heights of the electroplated bumps and reflowed bumps increased with a larger via, while the aspect ratio of bumps decreased. To obtain high density bumps, the bump pitch was decreased so that the nearest bumps touched. The touching between the nearest bumps occurred during the over-plating procedure but not during the reflowing procedure because the mushroom diameter formed by over-plating was larger than the reflowed bump diameter. This study demonstrated that an arrangement in zig-zag rows is effective in realizing flip chip interconnect bumps with both a high density and high aspect ratio.
A 10 Gb/s limiting amplifier IC with the emitter area of 1.5xlOpn1~ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this study. we evaluated fme pitch bump using WL-CSP (Wafer This paper describes the design and fabrication of lOGbps limiting amplifier using AIGaAdGaAs HBTs for the optical transmission system and the development of fme pitch WL-CSP process. Finally the frequency response and eye diagram of the limiting amplifier package module are discussed. Level-Chip Scale Packag-ing) instead of conventional wire bonding for interconnection. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the rise/fall times were about 9@s, and the output voltage swing was limited to 65OmV,, with input voltage ranging from 50 to 50OmV. The Small signal gains in wafer and package module were 16.25dB and 14.86dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 1.5dB up to 1OGHz. But, the characteristics of return loss was improved in package module. This is due to the short interconnection length by WL-CSP. In this study, we developed fine pitch bump with the 4 0 p m diameter and 100 p m pitch using WL-CSP process. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fme pitch pad.
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