Approaches for dealing with scheduling and load-balancing in PC-based cluster systems are famous and well known. In such environments, Self-Scheduling Schemes are suitable for parallel loops with independent iterations. However, while schemes such as FSS, GSS, and TSS fit most computer systems, they cannot provide good load-balancing. Chao-Tung Yang and Shun-Chi Chang proposed a parallel loop scheduling scheme for heterogeneous PC cluster systems in Yang and Chang [13]. Though the proposed scheme allows users to choose parameters before execution initialization, weaknesses in it motivated us to develop further improvements. For instance, using fixed and monotonous parameters can easily lead to invalid scheduling due to use of previously input information. Thus, in this paper we propose a new scheme that fits most widely available computer systems and allows the scheduling parameter to be adjusted dynamically in order to provide higher overall performance.
Abstract. The approaches to deal with scheduling and load balancing on PCbased cluster systems are famous and well-known. Self-scheduling schemes, which are suitable for parallel loops with independent iterations on cluster computer system, they have been designed in the past. In this paper, we propose a new scheme that can adjust the scheduling parameter dynamically on an extremely heterogeneous PC-based cluster and grid computing environments in order to improve system performance. A grid computing environment consists of multiple PC-based clusters is constructed using Globus Toolkit and SUN Grid Engine middleware. The experimental results show that our scheduling can result in higher performance than other similar schemes.
Low power has played an increasingly important role for embedded systems. To save power, lowering voltage and frequency is very straightforward and effective; therefore, dynamic voltage scaling (DVS) has become a prevalent lowpower technique. However, DVS makes no effect on power saving when the voltage reaches a lower bound. Fortunately, a technique called dynamic pipeline scaling (DPS) can overcome this limitation by switching pipeline modes at low-voltage level. Approaches proposed in previous work on DPS were based on hardware support. From viewpoint of compiler, little has been addressed on this issue. This paper presents a DPS optimization technique at compiler time to reduce power dissipation. The useful information of an application is exploited to devise an analytical model to assess the cost of enabling DPS mechanism. As a consequence, we can determine the switching timing between pipeline modes at compiler time without causing significant run-time overhead. The experimental result shows that our approach is effective in reducing energy consumption.
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