The porous nature of carbon nanotube (CNT) arrays allows for the unique opportunity to tailor their mechanical response by the infiltration and deposition of nano-scale conformal coatings. Here, we fabricate novel photo-lithographically defined CNT pillars that are conformally coated with amorphous silicon carbide (a-SiC) to strengthen the interlocking of individual CNTs at junctions using low pressure chemical vapour deposition (LPCVD). We further quantify the mechanical response by performing flat-punch nanoindentation measurements on coated CNT pillars with various high-aspect-ratios. We discovered new mechanical failure modes of coated CNT pillars, such as "bamboo" and brittle-like composite rupture as coating thickness increases. Furthermore, a significant increase in strength and modulus is achieved. For CNT pillars with high aspect ratio (1:10) and coating thickness of 21.4 nm, the compressive strength increases by an order of magnitude of 3, towards 1.8 GPa (from below 1 MPa for uncoated CNT pillars) and the elastic modulus increases towards 125 GPa. These results show that our coated CNT pillars, which can serve as vertical interconnects and 3D super-capacitors, can be transformed into robust high-aspectratio 3D-micro architectures with semiconductor device compatible processes.
A three-dimensional (3D) general coupling model for electromigration has been developed with the use of the mass conservation equation. The flux terms that include concentration gradient, electron wind force, stress migration, and thermal migration are considered. The constitutive equation for the electromigration strain has been derived. Then, the governing equations for one-dimensional (1D) metal lines are obtained for both totally fixed and stress-free mechanical boundary conditions. The numerical results reveal that the hydrostatic stress is significantly lower than the predicted results in the existing literature for the totally fixed configuration. Extensive discussions are presented to provide the explanations of such difference. The vacancy concentration gradient plays an important role in formulating electromigration problems. The current-driven flux can be entirely balanced by the concentration gradient that acts as an opposing force during electromigration under a stress-free condition in steady-state. The new solutions of the critical threshold jL, the product of current density, and metal line length are obtained in terms of vacancy concentration. As electromigration is eventually determined by the void growth, the critical vacancy concentration is used to reanalyze Blech's experiment data. The theoretical predictions are consistent with the experimental observations.
The wide bandgap of silicon carbide (SiC) has attracted a large interest over the past years in many research fields, such as power electronics, high operation temperature circuits, harsh environmental sensing, and more. To facilitate research on complex integrated SiC circuits, ensure reproducibility, and cut down cost, the availability of a low-voltage SiC technology for integrated circuits is of paramount importance. Here, we report on a scalable and open state-of-the-art SiC CMOS technology that addresses this need. An overview of technology parameters, including MOSFET threshold voltage, subthreshold slope, slope factor, and process transconductance, is reported. Conventional integrated digital and analog circuits, ranging from inverters to a 2-bit analog-to-digital converter, are reported. First yield predictions for both analog and digital circuits show great potential for increasing the amount of integrated devices in future applications.
A new panel-level silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) power module was developed by using the fan-out and embedded chip technologies. To achieve the more effective thermal management and higher reliability under thermal cycling, a new optimization method called Ant colony optimization-back propagation neural network (ACO-BPNN) was developed for optimizing SiC modules, and contrast it with the Response Surface Method (RSM). First, the heat dissipations of SiC MOSFET with different redistribution layer (RDL) materials were simulated through the ANSYS finite element simulation. Then, the RSM was adopted to design the experiments for optimization. Third, the optimized design considering both junction temperature and thermal-mechanical stress is obtained using RSM and ACO-BPNN. The results show that: 1) compared with nanosilver, copper has a relatively good heat dissipation effect, but nano-silver has a better thermodynamic performance, and 2) ACO-BPNN can provide more accurate optimization Manuscript
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