To enable fast and accurate models of SiC MOS-FETs for transient simulation, a hybrid data-driven modeling methodology of SiC MOSFETs is proposed. Unlike conventional modeling methods that are based on complex nonlinear equations, data-driven Artificial Neural Networks (ANNs) are used in this paper. For model accuracy, the I-V characteristics are measured in the whole operation region to train the ANN. The ANN model is then combined with behavior-based equations to model the cutoff region and to avoid overfitting the ANN. In addition, the C-V characteristics are modeled by ANNs with a logarithmic scale for accuracy. The proposed model is implemented and simulated in SPICE simulator SIMetrix. The simulation results are compared with experimental results from a double-pulse tester to validate the proposed modeling methodology. The model is also compared with the Angelov model created by the Keysight MOSFET modeling software. The comparison results show that the proposed model is more accurate than the Angelov model. Besides, when compared to the Angelov model, the proposed model requires 30% less computation time when simulating a double pulse tester. In addition, the proposed modeling method also has better adaptability to model different types of SiC MOSFETs.Index Terms-SiC MOSFET, transient model, hybrid modeling, artificial neural network.
The impact of the stress in room temperature inductively coupled plasma chemical vapour deposited (ICP-CVD) SiN x surface passivation layers on off-state drain (I DS-off) and gate leakage currents (I GS) in AlGaN/GaN high electron mobility transistors (HEMTs) is reported. I DS-off and I GS in 2 μm gate length devices were reduced by up to four orders of magnitude to ∼10 pA/mm using a compressively stressed bilayer SiN x passivation scheme. In addition, I on /I off of ∼10 11 and subthreshold slope of 68 mV/dec were obtained using this strain engineered surface passivation approach.
This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.In this work, we report the performance of 3 mm gate length "dual barrier" InAlN/AlGaN/GaN HEMTs on Si substrates with gate-drain contact separations in the range 4-26 mm. Devices with Pt-and Ni-based gates were studied and their leakage characteristics are compared. Maximum drain current I DS of $1 A mm À1 , maximum extrinsic transconductance g m $203 mS mm À1 and on-resistance R on $4.07 V mm for gate to drain distance L GD ¼ 4 mm were achieved. Nearly ideal subthreshold swing of $65.6 mV dec À1 was obtained for L GD ¼ 14 mm. The use of Pt-based gate metal stacks led to a two to three orders of magnitude gate leakage current decrease compared to Ni-based gates. The influence of InAlN layer thickness on the transistor transfer characteristics is also discussed.
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