Since strict defect control causes both the enhancement of manufacturing yield and the drop of machine operation rate, defect inspection paremeters should be optimized to minimize the production time for a fixed amount of ASIC chips. We propose new manufacturing model which takes account of not only inspection and yield model but also and workflow model. In this paper, as a first step, we study basic characteristics of our model affected by inspection conditions, defect situations and workflow conditions. The numerical experimental results demonstrated that many phenomenon can be calculated only by the model which takes account of both yield and workflow. For an example, control limit of defected die count should be increased about 50% when loading factor chages from 60% to 85%.
We propose a new and fast method for monitoring contact hole roughness (CHR), which can be a major yield-loss factor for advanced SRAMs. The method, defect-review scanning electron microscopy (SEM) image processing, can monitor CHR 100 times faster than the conventional method by critical dimension (CD)-SEM. The speed can facilitate faster identification of process countermeasures by, for example, making detailed monitoring of CHR variation within a wafer practicable. Results for CHR obtained by both new and conventional methods show similar trends for differences in process conditions. Also, we experimentally confirmed the new method's measuring variation of the rate of deformed contact holes.Through evaluation by the new method, we demonstrate that the standby electric current of advanced SRAM depends not only on overlay error but also on CHR. We believe that the new method will be very useful in the evaluation of process countermeasures and their stability.
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