We propose the notion of logical reliability for real-time program tasks that interact through periodically updated program variables. We describe a reliability analysis that checks if the given short-term (e.g., single-period) reliability of a program variable update in an implementation is sufficient to meet the logical reliability requirement (of the program variable) in the long run. We then present a notion of design by refinement where a task can be refined by another task that writes to program variables with less logical reliability. The resulting analysis can be combined with an incremental schedulability analysis for interacting real-time tasks proposed earlier for the Hierarchical Timing Language (HTL), a coordination language for distributed real-time systems. We implemented a logical-reliabilityenhanced prototype of the compiler and runtime infrastructure for HTL.
Abstract-We take the paradigm of cloud computing developed in the cyber-world and put it into the physical world to create a cyber-physical computing cloud. A server in this cloud moves in space making it a vehicle with physical constraints. Such vehicles also have sensors and actuators elevating mobile sensor networks from a deployment to a service. Possible hosts include cars, planes, people with smartphones, and emerging robots like unmanned aerial vehicles or drifters. We extend the notion of a virtual machine with a virtual speed and call it a virtual vehicle, which travels through space by being bound to real vehicles and by migrating from one real vehicle to another in a manner called cyber-mobility. We discuss some of the challenges and envisioned solutions, and describe our prototype implementation.
AbsttactAn advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61prrP with conventional 1-line lithography and 7.32pm2 with 1-line phaseshift lithography. The process features PELOX isolation to provide a 1 .Opm active pitch, MOSFET transistors designed for a 0.80p.m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thinfilm polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance. IntroductionFast. hiah density static RAMS rewire both a small bitcell area an( a high'performance piocess. At thel6Mb generation, a bitcell area of less than 9.Op.rn2 can be achieved using 1-line technology with multiple layers of polysilicon and self-aligned contacts. Use of phase-shift lithography provides for even smaller bitcell areas. A symmetrical split word-line bitcell and thin film polysilicon transistors serve to enhance cell stability. Speed requirements can be met by adding a high performance, double polysilicon bipolar transistor. With careful design, bipolar parasitic capacitances can be even further reduced without increasing process complexity. With the aggressive scaling of bitcell areas at the 4Mb generation and beyond, SER has become a primary reliability concern for SRAMs. In this technology, a quadruple-well has been developed to provide diode isolation for the memory array while allowing for simultaneous optimization of MOSFETs and bipolars.
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