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We propose a field-free switching SOT-MRAM concept that is integration friendly and allows for separate optimization of the field component and SOT/MTJ stack properties. We demonstrate it on a 300 mm wafer, using CMOScompatible processes, and we show that device performances are similar to our standard SOT-MTJ cells: reliable sub-ns switching with low writing power across the 300mm wafer. Our concept/design opens a new area for MRAM (SOT, STT and VCMA) technology development. Introduction: Among non-volatile memory technologies, Spin-Transfer-Torque (STT) MRAM is seen as a credible candidate to replace SRAM in low level caches due to its scalability, low power and high speed, as well as compatibility with scaled CMOS processes and voltages. This is reflected by major foundries and tool suppliers investing significant R&D resources into embedded MRAM past years. Recently they even started prototyping demonstrators, progressively reaching maturity for mass production [1-5]. However, STT-MRAM

The voltage-gate-assisted spin-orbit-torque (VGSOT) writing scheme combines the advantages from voltage control of magnetic anisotropy (VCMA) and spin-orbit-torque (SOT) effects, enabling multiple benefits for magnetic random-access-memory (MRAM) applications. In this work, we give a complete description of the VGSOT writing properties on perpendicular magnetic tunnel junction (PMTJ) devices, and we propose a detailed methodology for their electrical characterization. The impact of gate assistance on the SOT switching characteristics is investigated using electrical pulses down to 400 ps. The VCMA coefficient (ξ ) extracted from the current-switching scheme is found to be the same as that from the magnetic-field-switch method, which is in the order of 15 fJ/Vm for 80-150-nm devices. Moreover, as expected from the pure electronic VCMA effect, ξ is revealed to be independent of the writing speed and gate length. We observe that SOT switching current characteristics are modified linearly with gate voltage (V g ), similar to that for the magnetic properties. We interpret this linear behavior as the direct modification of perpendicular magnetic anisotropy induced by VCMA. At V g = 1 V, the SOT write current is decreased by 25%, corresponding to a 45% reduction in total energy down to 30 fJ/bit at 400 ps speed for the 80-nm devices used in this study. To test the operation reliability, we investigate the gate-SOT pulse configurations and overlays, and we find that an extended gate duration is able to preserve maximized gate benefit and selectivity. Furthermore, the device-scaling criteria are proposed, and we reveal that the VGSOT scheme is of great interest, as it can mitigate the complex material requirements of achieving high SOT and VCMA parameters for scaled MTJs. Finally, we perform design-to-technology co-optimization analysis to show that VGSOT MRAM can enable high-density arrays close to two-terminal geometries, with high-speed performance and low-power operation, showing great potential for embedded memories as well as in memory computing applications at advanced technology nodes.

Switching induced by spin-orbit torque (SOT) is being vigorously explored, as it allows the control of magnetization using an in-plane current, which enables a three-terminal magnetic-tunnel-junction geometry with isolated read and write paths. This significantly improves the device endurance and the read stability, and allows reliable subnanosecond switching. Tungsten in the β phase, β-W, has the largest reported antidamping SOT charge-to-spin conversion ratio (θ AD ≈ −60%) for heavy metals. However, β-W has a limitation when one is aiming for reliable technology integration: the β phase is limited to a thickness of a few nanometers and enters the α phase above 4 nm in our samples when industryrelevant deposition tools are used. Here, we report our approach to extending the range of β-W, while simultaneously improving the SOT efficiency by introducing N and O doping of W. Resistivity and XRD measurements confirm the extension of the β phase from 4 nm to more than 10 nm, and transport characterization shows an effective SOT efficiency larger than −44.4% (reaching approximately −60% for the bulk contribution). In addition, we demonstrate the possibility of controlling and enhancing the perpendicular magnetic anisotropy of a storage layer (Co-Fe-B). Further, we integrate the optimized W(O, N) into SOT magnetic random-access memory (SOT-MRAM) devices and project that, for the same thickness of SOT material, the switching current decreases by 25% in optimized W(O, N) compared with our standard W. Our results open the path to using and further optimizing W for integration of SOT-MRAM technology.