This paper describes integration of an advanced composite high-K gate stack (4nm TaSiO x -2nm InP) in the In 0.7 Ga 0.3 As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (t OXE ) and low gate leakage (J G ) and (ii) effective carrier confinement and high effective carrier velocity (V eff ) in the QW channel. The L G =75nm In 0.7 Ga 0.3 As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750μS/μm and high drive current of 0.49mA/μm at V DS =0.5V.

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In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (L SIDE ) of 5nm are reported for the first time. The high-K gate dielectric formed on this non-planar device structure has the expected thin T OXE of 20.5Å with low J G , and high quality gate dielectric interface. The simplified S/D scheme is needed for the non-planar architecture while achieving significant reduction in parasitic resistance. Compared to the planar high-K InGaAs QWFET with similar T OXE , the non-planar, multi-gate InGaAs QWFET shows significantly improved electrostatics due to better gate control. The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III-V QWFETs for low power logic applications. IntroductionNon-planar, multi-gate architectures have been investigated for improved electrostatics in Si MOSFETs [1], and most recently in III-V MOSFETs [2]. In this work, nonplanar, multi-gate InGaAs QWFETs with high-K gate dielectric and ultra-scaled L SIDE of 5nm are reported. These non-planar, multi-gate QWFET devices have undoped InGaAs channel in the shape of a "fin" formed on top of large band gap InAlAs barrier, with simplified n ++ InGaAs source/drain scheme. Compared to the planar high-K InGaAs QWFET with similar electrical oxide thickness (T OXE ), the non-planar, multi-gate QWFET devices in this work show (i) more enhancement-mode threshold voltage (V T ) and (ii) significantly improved electrostatics with reducing transistor gate length (L G ) due to stronger gate control of the channel. In addition, the ultra-scaled L SIDE combined with the simplified n ++ InGaAs source/drain (S/D) scheme will enable device footprint scaling.

This research work demonstrates, for the first time, that the material quality of MOVPE III-V QWFET structures on Si can be matched to that of the best MBE III-V QWFET structures on Si. The MOVPE grown In 0.53 Ga 0.47 As QW layer on Si exhibits high Hall mobility of ~8000cm 2 /V-s at 300K, matching that obtained by MBE growth on lattice matched InP (the "gold standard"). IntroductionHigh mobility III-V semiconductors are of interest for transistor channel material applications for high performance and low power logic devices [1-6]. Direct epitaxial growth of such materials on Si substrates is desirable for heterogeneous integration with Si CMOS technology, while avoiding the need for large diameter (≥ 300mm) III-V substrates. However, this poses serious challenges due to the large lattice constant mismatch (e.g. 8% for In 0.53 Ga 0.47 As), coefficient of thermal expansion mismatch, and the generation of polar/non-polar interfaces between III-V and Si. These challenges are being addressed by the use of III-V buffer layer growth, either on blanket [7-10] or on patterned Si wafers [11], which reduces the number of defects reaching active device layers. Most of the research so far has used molecular beam epitaxy (MBE), which offers excellent process control; however, this technique is line-of-sight and non-selective, which poses challenges for process integration and conformal growth on non-planar 3D devices [2]. In contrast, metal organic vapor phase epitaxy (MOVPE) offers the twin advantages of (a) selective area growth and (b) growth on 3-D structures (conformality). To date there have been few studies [8] of MOVPE's feasibility for III-V film growth on Si for logic device applications, and no direct comparisons to MBE have been made. In this work, an InGaAs III-V quantum well field-effect transistor (QWFET) structure [4] (Fig. 1) is used to compare MOVPE and MBE growth processes, demonstrating for the first time that MOVPE III-V material quality can be matched to MBE.

Perhaps the greatest challenge facing quantum computing hardware development is the lack of a high throughput electrical characterization infrastructure at the cryogenic temperatures required for qubit measurements. In this article, we discuss our efforts to develop such a line to guide 300mm spin qubit process development. This includes (i) working with our supply chain to create the required cryogenic high volume testing ecosystem, (ii) driving full wafer cryogenic testing for both transistor and quantum dot statistics, and (iii) utilizing this line to develop a quantum dot process resulting in key electrical data comparable to that from leading devices in literature, but with unprecedented yield and reproducibility.