This study presents coupling of a poly(dimethylsiloxane) (PDMS) micro-chip with electrospray ionization-mass spectrometry (ESI-MS). Stable electrospray is generated directly from a PDMS micro-channel without pressure assistance. Hydrophobic PDMS aids the formation of a small Taylor cone in the ESI process and facilitates straightforward and low-cost batch production of the ESI-MS chips. PDMS chips were replicated with masters fabricated from SU-8 negative photoresist. A novel coating, an amorphous diamond-like carbon-poly(dimethylsiloxane) hybrid, deposited on the masters by the filtered pulsed plasma arc discharge technique, improved significantly the lifetime of the masters in PDMS replications. PDMS chip fabrication conditions were observed to affect the amount of background peaks in the MS spectra. With an optimized fabrication process (PDMS curing agent/silicone elastomer base ratio of 1/8 (w/w), curing at 70 degree C for 48 h) low background spectra were recorded for the analytes. The performance of PDMS devices was examined in the ESI-MS analysis of some pharmaceutical compounds and amino acids.
We show that gallium-ion-implanted silicon serves as an etch mask for fabrication of high aspect ratio nanostructures by cryogenic plasma etching (deep reactive ion etching). The speed of focused ion beam (FIB) patterning is greatly enhanced by the fact that only a thin approx. 30 nm surface layer needs to be modified to create a mask for the etching step. Etch selectivity between gallium-doped and undoped material is at least 1000:1, greatly decreasing the mask erosion problems. The resolution of the combined FIB-DRIE process is 20 lines microm(-1) with the smallest masked feature size of 40 nm. The maximum achieved aspect ratio is 15:1 (e.g. 600 nm high pillars 40 nm in diameter).
Today's supercapacitor energy storages are typically discrete devices aimed for printed boards and power applications. The development of autonomous sensor networks and wearable electronics and the miniaturisation of mobile devices would benefit substantially from solutions in which the energy storage is integrated with the active device. Nanostructures based on porous silicon (PS) provide a route towards integration due to the very high inherent surface area to volume ratio and compatibility with microelectronics fabrication processes. Unfortunately, pristine PS has limited wettability and poor chemical stability in electrolytes and the high resistance of the PS matrix severely limits the power efficiency. In this work, we demonstrate that excellent wettability and electro-chemical properties in aqueous and organic electrolytes can be obtained by coating the PS matrix with an ultra-thin layer of titanium nitride by atomic layer deposition. Our approach leads to very high specific capacitance (15 Fcm -3 ), energy density (1.3 mWhcm -3 ) , p o w e r d e n s i t y ( u p t o 2 1 4 W c m -3 ) and excellent stability (more than 13,000 cycles). Furthermore, we show that the PS-TiN nanomaterial can be integrated inside a silicon chip monolithically by combining MEMS and nanofabrication techniques. This leads to realisation of in-chip supercapacitor, i.e., it opens a new way to exploit the otherwise inactive volume of a silicon chip to store energy.
We demonstrate a fabrication method for high-performance field-effect transistors (FETs) based on dry-processed random single-walled carbon nanotube networks (CNTNs) deposited at room temperature. This method is an advantageous alternative to solution-processed and direct CVD grown CNTN FETs, which allows using various substrate materials, including heat-intolerant plastic substrates, and enables an efficient, density-controlled, scalable deposition of as-produced single-walled CNTNs on the substrate directly from the aerosol (floating catalyst) synthesis reactor. Two types of thin film transistor (TFT) structures were fabricated to evaluate the FET performance of dry-processed CNTNs: bottom-gate transistors on Si/SiO2 substrates and top-gate transistors on polymer substrates. Devices exhibited on/off ratios up to 10(5) and field-effect mobilities up to 4 cm(2) V(-1) s(-1). The suppression of hysteresis in the bottom-gate device transfer characteristics by means of thermal treatment in vacuum and passivation by an atomic layer deposited Al(2)O(3) film was investigated. A 32 nm thick Al(2)O(3) layer was found to be able to eliminate the hysteresis.
We present thermal detectors based on 40 nm-thick strain tuned single crystalline silicon membranes shaped into a heater area supported by narrow n- and p-doped beams, which also operate as a thermocouple. The electro-thermal characterization of the devices reveals a noise equivalent power of 13 pW/Hz1/2 and a thermal time constant of 2.5 ms. The high sensitivity of the devices is due to the high Seebeck coefficient of 0.39 mV/K and reduction of thermal conductivity of the Si beams from the bulk value. The performance enables fast and sensitive detection of low levels of thermal power and infrared radiation at room temperature. The devices operate in the Johnson-Nyquist noise limit of the thermocouple, and the performance improvement towards the operation close to the temperature fluctuation limit is discussed.
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