A wafer level dielectric breakdown reliability measurement technique using logarithmically stepped‐up stress current density is proposed, and the effectiveness of this technique is demonstrated. The stepped current time‐dependent dielectric breakdown (SCTDDB) measurement starts at a very low stress current density
false(10−5A/cm2false)
, and it steps up logarithmically to a maximum stress current density
false(1.0A/cm2false)
until oxide breakdown occurs. The SCTDDB measurement has high detection sensitivity for defect‐related breakdown, a wide dynamic range
false(10−5 normalto 102C/cm2false)
, adequate measurement time (within
60 normals/normalchip
), and data compatibility with conventional constant current TDDB result. The SCTDDB technique is a very simple and powerful evaluation tool for thin silicon dioxide reliability analysis.
The wafer expansion scaling error in overlay accuracy using a stepper has been investigated. The scaling error depends on the exposure energy, mask aperture ratio and wafer surface reflectance. The scaling error is observed only along the X axis when using a global alignment method. From the experimental results, we present a mechanism which explains the scaling error. Then the occurrence of the scaling error according to the mechanism is simulated by the heat conduction and displacement analysis. The cause of the scaling error is proved to be local wafer expansion due to the accumulated heat generated by the exposure light energy.
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