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A copper hillock induced interconnect failure mechanism is presented. The copper hillock is frequently generated during a copper dual damascene process and hillock formation is found to degrade the interconnect integrity by affecting the following process steps. The copper hillock appears to damage the SiN capping layer and results in copper corrosion during via etch. The corrosion generates copper particles inside via holes and the defects are found to make the following metal depositions incomplete during via formation. Based on the observations, a copper hillock induced defect model is proposed and a new copper process is suggested to reduce copper hillocks.

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In recent years, model based verification for optical proximity effect correction (OPC) has become one of the most important items in semiconductor industry. Major EDA companies have released various softwares for OPC verification. They have continuously developed and introduced new methods to achieve more accurate results of OPC verification. The way to detect only real errors by excluding false errors is the most important thing for accurate and fast verification process, because more time and human resource are needed to inspect the result of verification as increasing false errors. A major source of false errors is bending patterns. The number of those from bending patterns is over thousands and they are inevitable. The most verification tools have the scheme for excluding those by using CD error non-checking or filtering area. Real errors around bending pattern will not be able to detect with too big size of area, while too many false error will be reported with too small size of area. Since currently most verification tools had only a fixed area size for filtering, it has been impossible to achieve most accurate and efficient verification results. Through the optimization of area size with different corner length, we could get more accurate and efficient results and decrease the time for review to find real errors. In this paper, the suggestion in order to increase efficiency of OPC verification process by using different size of CD error non-checking area with various corner lengths is presented.

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