The study for increasing efficiency of OPC verification by reducing false errors from bending pattern by using different size of CD error non-checking area with various corner lengths

Abstract

In recent years, model based verification for optical proximity effect correction (OPC) has become one of the most important items in semiconductor industry. Major EDA companies have released various softwares for OPC verification. They have continuously developed and introduced new methods to achieve more accurate results of OPC verification. The way to detect only real errors by excluding false errors is the most important thing for accurate and fast verification process, because more time and human resource are needed to inspect the result of verification as increasing false errors. A major source of false errors is bending patterns. The number of those from bending patterns is over thousands and they are inevitable. The most verification tools have the scheme for excluding those by using CD error non-checking or filtering area. Real errors around bending pattern will not be able to detect with too big size of area, while too many false error will be reported with too small size of area. Since currently most verification tools had only a fixed area size for filtering, it has been impossible to achieve most accurate and efficient verification results. Through the optimization of area size with different corner length, we could get more accurate and efficient results and decrease the time for review to find real errors. In this paper, the suggestion in order to increase efficiency of OPC verification process by using different size of CD error non-checking area with various corner lengths is presented.

New Design Based Metrology for Fast Detection of Crucial Lithographic Defects

“…There has been increased interest in DBMs to control gate critical dimension (CD). 4,5) We use NGR2100Ô as a DBM tool that can measure the CD through full chip real pattern. This is useful to verify OPC accuracy, systematic defects, and hot spot improvements.…”

“…The geometry verification system (GVS) is designed to detect defects in a pattern at an early stage in the semiconductor manufacturing process. It does so by directly comparing the scanning electron microscopy (SEM) image, which is produced using an electron beam, to computer aided design (CAD) data, 5) which is pattern design data, between multiple shots. Nondestructive inspection by NGR2100Ô allows faults during semiconductor processing, such as repeated defects, to be detected.…”