Negative bias temperature instability (NBTI) of pMOSFETs with ultra-thin gate dielectrics was investigated from four points of view: basic mechanism of NBTI, dependence of NBTI on gate dielectric thickness, mechanism of NBTl enhancement caused by addition of nitrogen to the gate dielectrics, and possibility of applying SiON gate dielectrics with a high concentration of nitrogen. By investigating the behavior of FET characteristics after NBT stresses were stopped, it was clarified that a portion (60%, in our case) of hydrogen atoms released by the NBT stress remain in the gate dielectric in the case of a 1.85-nm-thick NO-oxynitride gate dielectric. The existence of the hydrogen was shown to lead to the generation of. positive fixed charges in the gate dielectric. It was also found that NBTI depends little on gate dielectric thickness. Moreover, we revealed that the origin of NBTl enhancement by incorporating nitrogen into gate dielectrics is the property of attracting H,O or OH. We speculate this property of attracting H,O or OH is due to the existence of positive fixed charges induced by undesirable nitrogen. We evaluated NBTl immunity of SiN gate dielectrics with oxygen-enriched interface (01-SiN) in which high carrier mobility was obtained by reducing positive fixed charges. The 01-SiN gate dielectrics with EOTs of 1.4 and 1.6 nm were found to have sufticient.lifetime for practical use under 1 V operation.
The influence of line-edge roughness (LER) on transistor performance was investigated experimentally and the preciously proposed guideline for CD and LER measurements was examined.First, regarding the transistor-performance measurements, a shift of roll-off curves caused by LER within a gate pattern was observed. Moreover, the effect of transistor-width fluctuation originating from long-period LER was found to cause a variation in transistor performance. Second, regarding LER and CD metrology, the previously reported guideline was validated by using KrF and ArF resist-pattern samples. It was found that both CD and LER should be evaluated with the 2-µm-long inspection area. Based on this guideline, a comprehensive approach for evaluating LER and CD for transistor fabrication process is presented. The authors consider that this procedure can provide useful information for the 65-nm-node technology and beyond.
In short-channel CMOS devices with extension structures, current crowding was found to occur in the source extension, significantly degrading current drivability. Reducing this effect by using high-dose extensions and low parasitic capacitance provided by a localized punchthrough stopper layer produced high drivability, enabling a sub-10-ps CMOS gate delay to be attained.
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