A b s t r a c tWe have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640 x 480) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI uses compression ratio control to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer so that it can process signals at high speed without using high-speed image memory. The JPEG codec core is small (40,000 gates) and power consumption is low (220 mW) for broader application in image processing in consumer markets.
. I n t r o d u c t i o n JPEG (Joint Photographic Expert Group [I])-relatedLSls are now being used in a wide range of multimedia applications, including digital still cameras and video capture systems. With features like easiness of editing, there appear the JPEG systems which can handle not only still images but motion pictures (called motion JPEG). One such application is PC video capture systems where the commercialization of multimedia is generating some rather intense product cost competition. At the same time, the advent of more advanced digital still camera functions, such as higher resolution, continuous shot capability and compatibility with motion pictures, has further emphasized the need for downsizing mounting areas and reducing power consumption. These are driving the demand for lower cost and higher performance in JPEG signal processing.JPEG signals are conventionally processed either through software using processors, or through hardware using dedicated LSI chips. Therefore the demand for higher performance such as compatibility with highresolution motion pictures in the former case requires more expensive CPUs, or in the latter case requires more chips in dedicated LSls(ex. [Z]). In either case, this makes reducing system cost extremely difficult.In order to overcome the cost issue, we developed a hard-wired single-chip JPEG codec LSI that has low power requirements and is multifunctional. In addition to 0-7803-3669-0 $5.00 0 1997 IEEE I 1 offering functions like video capture and output, the LSI also features algorithmic functions like memory compression and compression ratio control that help to bring down cost. The following describes algorithmic functions and technical developments for the LSI 2 . C h i p F e a t u r e A motion JPEG encoder/decoder was integrated on the single chip. The chip does not require an external processor because it can compress and decompress simply by connecting a single DRAM chip that serves as external memory.It can compress and decompress both 640 pixel x 480 line (VGA size) images at 30 frames per second(fps) and still pictures measuring 2048 x 2048 as well. With video output compatible with NTSC and PAL formats as well as interlaced and non-interlaced formats, the chip is ideal for applications like digital still cameras and amusement equipment.
N e w T e c h n i c a l D e v e l o p m e n t sNewly developed technologies featured in the LSI chip are d...
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