In this paper; a baseline JPEG encoder soft Intellectual Property (IP) is proposed together with a memory efJicient preprocessing architecture for scanner to solve the bandwidth problem between PC and scunner. This JPEG IP features that its quantization tables are re-configurable ut run time and compile time. It is a modularized andfully pipelined design with friendly interface, which makes it easier to be integrated into various application systems. It is silicon proven to run up to 40MHz at 3.3V With the optimized preprocessing unit feeding data smoothly into JPEC core, it is a low cost and cotnpetitive solution for scunner to have compression ,function embedded. \ follows. In section 11, the proposed JPEG soft IP is introduced. Then memory efficient architecture for preprocessing unit is described in section 111. Design and simulation results are shown in section IV, and finally the conclusion is given in section V.