Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-m HV process to provide high ESD level with high holding voltage for HV applications. In addition, the guard-ring layout on the stacked LV PMOS devices was further investigated in silicon chip to get high ESD robustness and latchup-free immunity for HV applications. I. INTRODUCTIONElectrostatic discharge (ESD) may occur accidentally during the fabrication, package, and assembling processes of IC products, which often caused serious damages on ICs. High-voltage (HV) ICs were found with bad ESD robustness [1]- [2]. Lateral DMOS (LDMOS) was often used as ESD protection device in HV process, but the holding voltage (V h ) of LDMOS after snapback was smaller than the circuit operating voltage (V CC ) [3]- [4]. During normal circuit operation, the noise might unpredictably trigger the parasitic BJT of the ESD devices, and the supply voltage (V CC ) keeps the parasitic BJT to be continually turned on. Such on-chip ESD device would be burned out after a period of time, under the circuit normal operating condition. Thus, the LDMOS was sensitive to latchup issue.The typical I-V characteristics of ESD protection devices are illustrated in Fig. 1. Breakdown voltage (V BD ) and supply voltage (V DD or V CC ) of the internal circuits divide the plot into three parts. The middle part is the desired ESD protection window. The green curve is an example of the desired ESD device's I-V characteristics. To get an effective ESD protection, the trigger voltage (V t1 ) should be smaller than breakdown voltage of the internal circuits. Furthermore, to avoid latchup issue, the holding voltage (V h ) should be larger than the supply voltage of the internal circuits. The onresistance of an ESD protection device should be as small as possible to get a high ESD robustness. The I-V characteristics of ESD devices should fit into this window for both effective ESD protection and latchup-free design. Therefore, the stacked configuration of LV devices is a way to achieve a high holding voltage for ESD protection in HV circuits [5]- [7]. The schematic of stacked LV PMOSs for HV ESD protection are illustrated in Fig. 2(a). The holding voltages of stacked LV PMOSs with different stacking numbers can be found in Fig. 2(b). The total holding voltage of stacked PMOSs is the multiple of the holding voltage of single PMOS. The total trigger voltage of stacked PMOSs is also the multiple of the
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