Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ Line

He, Chang-Yuan; Tang, Kai-Neng; Chen, T. S.; Chang, Kuang-Yi; Lin, Cheng-Kuan; Sato, K.; Jou, Shyh-Jye; Chen, Po-Hsiang; Chen, H. M.; Rong, Bor-Doou; Itoh, K.

doi:10.1109/a-sscc47793.2019.9056897

2019 IEEE Asian Solid-State Circuits Conference (A-Sscc) 2019

DOI: 10.1109/a-sscc47793.2019.9056897

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Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ Line

Chang-Yuan He

Kai-Neng Tang

T. S. Chen

et al.

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Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ Line

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