A tri-layer soft reflow fabrication method using solvent vapour that resulted in a sub-micrometer resonant tunneling diode is reported in details. The processing steps are simple, time efficient and are all based on conventional i-line photolithography. The tri-layer soft reflow technique is able to shrink the emitter lateral width from 1µm down to 0.35µm (65% reduction) using a solvent at a very low temperature (<50 ˚C). Studies of device's peak current density (J P ) suggests that excellent scalability is achieved as the emitter area reduces from ~29µm 2 down to ~0.5µm 2 with no significant increase in peak voltage (V P ) due to high series resistance normally associated with submicrometer dimensions. The valley current (I V ) however increases due to side-wall damage introduced by the reactive ion etching (RIE) process. As a result, the peak-tovalley-current ratio (PVCR) decreases from 5.0 (6.3) to 3.8 (4.1) in forward (reverse) direction as the emitter area decreases. We therefore successfully demonstrated the fabrication of a sub-micrometer RTD by using a tri-layer soft reflow technique that has the benefit of excellent scalability, high throughput, repeatable and a reliable low cost process.
We report a new and simple low temperature soft reflow process using solvent vapour. The combination of this soft reflow and conventional i-line lithography enables low cost, highly efficient fabrication at the deep-submicron scale. Compared to the conventional thermal reflow process, the key benefits of the new soft reflow process are its low temperature operation (<50 °C), greater shrinkage of the structure size (up to 75%) and better controllability. Gate openings reflowed from 1 μm to 250 nm have been routinely and reproducibly achieved by utilizing the saturation characteristics of the process. The feasibility of this soft reflow process is demonstrated in the fabrication of a 350 nm T-gate pseudomorphic high electron mobility transistor. By shrinking the gate length by a factor of three (from a 1 μm initial opening), the output current is improved by 60% (500 mA mm(-1) from 300 mA mm(-1)) and f(T) and f(MAX) are increased to 70 GHz (from 20 GHz) and 120 GHz (from 40 GHz) respectively. The proposed soft reflow could potentially be applied on other compatible substrates such as polymer based material for organic or thin film devices, potentially leading to many new possible applications.
This work described the fabrication and performances of strained channel In 0.52 Al 0.47 As/In 0.7 Ga 0.3 As/InP pHEMTs with thermally evaporated Pd/Ti/Au gate metallization. The electrical characteristics of these Pd-gate devices are studied to investigate the effects of changing the Pd metal thickness, annealing temperature and annealing time. Following annealing at 200 • C for 35 min, a 10 nm Pd-gate device displays a V TH of −0.25 V, which is significantly smaller compared to those with Ti/Au gate schemes showing V TH = −0.75 V. A 1 um gate length device exhibits an improved Gm of 580 mS mm −1 (from 500 mS mm −1 ), a high I DSmax of 400 mA mm −1 (from 330 mA mm −1 ) and good f T and f max of 24.5 and 49 GHz commensurate with the 1 μm gate length. All these enhancements are attributed to the controllable gate sinking of Pd. The device shows no significant degradation even after annealing at 230 • C for more than 5 h, which implies that the reliability of these Pd-gate structures is excellent.
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