The design and architectures of a microcode-based memory BIST and programmable FSM-based memory BIST unit are p r esented. The proposed microcode-based memory BIST unit is more e cient and exible than existing architectures. Test logic overhead of the proposed programmable versus non-programmable memory BIST architectures is evaluated. The proposed p r ogrammable memory BIST architectures could be used to test memories in di erent stages of their fabrication and therefore result in lower overall memory test logic overhead. We show that the proposed microcode-based memory BIST architecture has better extendibility and exibility while having less test logic overhead than the programmable FSM-based memory BIST architecture. Last Address Instruction 1 Instruction 2 Instruction 3 Instruction n Y bits Z bits Instruction Counter Branch Register log2(Z) Instruction Address Instruction Decode Module Reset to Branch Register Reset to 0; Reset to 1 Registers Reference Instruction(7-9) Instruction(1,3,4) Reset Instruction(0-9)
The development of two programmable memory BIST architectures is rst reported. A memory synthesis framework which can automatically generate, verify and insert programmable as well as non-programmable BIST units is developed as a vehicle to e ciently integrate BIST architectures in today's memory-intensive systems. Custom memory test algorithms could be l o aded in the developed p r ogrammable BIST unit and therefore any type of memory test algorithm could be r ealized. The exibility and e ciency of the framework are demonstrated b y showing that these memory BIST units could be generated, functionally veri ed and inserted in a short time.
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