Defect analysis and realistic fault model extensions for static random access memories

Zarrineh, K.; Deo, Ankita; Adams, R.D.

doi:10.1109/mtdt.2000.868625

Cited by 9 publications

(8 citation statements)

References 6 publications

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“…Sense Amplifier: Sense amplifier faults in semiconductor memories have been well studied [45,46]. They can be divided into static and dynamic faults.…”

Section: Fault Modeling For Some Peripheral Circuitsmentioning

confidence: 99%

Testing Computation-in-Memory Architectures Based on Emerging Memories

Hamdioui

Fieback

Nagarajan

et al. 2019

2019 IEEE International Test Conference (ITC)

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Today's computing architectures and device technologies are becoming incapable of meeting the increasingly stringent demands on energy and performance posed by evolving applications. Therefore, alternative novel post-CMOS computing architectures are being explored. Some of these are Computationin-Memory (CIM) architectures based on memristive devices; they integrate the processing units and the storage in the same physical location (i.e., the memory based on memristive devices). Due to their advanced manufacturing processes, use of new materials, and dual functionality, testing such chips requires specific schemes and therefore special attention. This paper describes the need for testing CIM architectures, proposes a systematic test approach, and shows the strong dependency of the test solutions on the nature of the architecture. All of these will be demonstrated using a design that is designed for computationin-memory bit-wise logical operations.

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“…Sense Amplifier: Sense amplifier faults in semiconductor memories have been well studied [45,46]. They can be divided into static and dynamic faults.…”

Section: Fault Modeling For Some Peripheral Circuitsmentioning

confidence: 99%

Testing Computation-in-Memory Architectures Based on Emerging Memories

Hamdioui

Fieback

Nagarajan

et al. 2019

2019 IEEE International Test Conference (ITC)

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“…In [7], the analysis of the defects based on charge is reported, and the measurement of some charge information of the faulty flip-flop is presented. In [8][9][10], the authors analyze the resistance effect in the memory circuit and provide the simulation waveform and useful results. All the previous studies stress functional fault coverage and defect coverage using existing test algorithms.…”

Section: Introductionmentioning

confidence: 99%

Defect oriented fault analysis for SRAM

Huang

Chou

2003

Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-0

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Fault analysis is an important step in establishing detailed fault models for subsequent diagnostics and debugging of a semiconductor memory product. We have performed defect injection in the memory cell array of an industrial SRAM circuit and analyzed the faulty behavior with respect to each defect injected. We found that although some of the defects can be mapped to existing fault models, there are many defects that result in unmodeled faults. Moreover, a defect may exhibit a different faulty behavior at a different location in the cell array. The voltage and temperature parameters can also change the faulty behavior. The simulation results show that almost all open and short defects lead to stuck-at faults, transition faults, and data retention faults.

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“…In this paper, we extend our previous work on defect analysis and fault model extensions for single-port static SRAM [11]. We find that existing tests for single-port memories are insufficient in that they do not give a complete coverage of defects in multi-port memories.…”

Section: Introductionmentioning

confidence: 55%

Defect analysis and a new fault model for multi-port SRAMs

Nagaraj

Upadhyaya²,

Zarrineh³

et al.

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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Semiconductor memory failures depend on the behavior of its components. This paper deals with testing of defects occurring in the memory cells of a multi-port memory. We also consider the resistive shorts between word/bit lines of same and different ports of the memory. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of patterns. Not only have existing models been taken into account in our simulation but also a new fault model for the multi-port memory is introduced. The boundaries of failure for the proposed defects are identified.

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Defect analysis and realistic fault model extensions for static random access memories

Cited by 9 publications

References 6 publications

Testing Computation-in-Memory Architectures Based on Emerging Memories

Testing Computation-in-Memory Architectures Based on Emerging Memories

Defect oriented fault analysis for SRAM

Defect analysis and a new fault model for multi-port SRAMs

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