In our integration scheme, a “pseudo-3D” capacitor cell is used where the TiAlN\Ir\IrO2\Pt bottom electrode is patterned before SBT deposition. In order to understand how this system behaves mechanically, we have investigated the evolution of the stress of blanket Sr1-xBi2+yTa2O9 (x, y < 0.5) layers deposited on this pre-patterned bottom electrode stack. SBT was deposited by metal organic vapor deposition (MOCVD) between 405 °C and 440 °C. The stresses were monitored by the change in the radius of curvature of the wafer at the subsequent processing steps: deposition of electrodes and SBT, crystallization and recovering annealing, and after removal of Pt top electrode, SBT and bottom electrode layers by dry etching. The stress conditions observed for the different planar layers as a function of the SBT deposition temperature was correlated to the TiAlN lateral oxidation length observed in the etched structure after the SBT crystallization step.
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