Although dropping the supply voltage below 2V is effective in reducing power consumption of LSIs for low-power systems, it has not been adopted because it severely degrades the system performance. This paper reports an experimental 1.2V mixed analoddigital LSI based on 0.3pm laterally-doped buried-layer (LDR) CMOS with 20.4V threshold voltages [l]. Based on circuits such as a double feedforward phase-compensated amplifier and a self current cut-off sense amplifier, a 9b 2MHz 4mW pipelined A/D converter, a 16kb 2mW SRAM with 32ns access time, and a basic logic gate with a 400ps delay and 0.4pW/MHz dissipation are realized.
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