Complementary high-voltage drain extended (DE) MOS transistors were implemented into TI's state-of-the-art production advanced analog and digital 1.5 -1.8V CMOS technology [1, 2]. These transistors allow for 5V drain operating voltage using the core gate oxide and have breakdown voltages, BVdss>10V. Experimental results along with Suprem and Medici simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses nwell as a drain extension. Experimental test results of Ids(Vds,Vgs), Igs(Vds), and BV(L) plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no cost adder.
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