In this paper we propose a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics. For main-mode bits, leakage current can be attributed to junction thermal-generation leakage current. For tail-mode bits, it is found for the first time that Gate-Induced Drain Leakage (GIDL) current has a dominant impact. The root cause is electric field enhancement caused by metal precipitates located at the gate-drain overlap region.
Etching characteristics of Si1−xGex alloys in ammoniac wet cleaning (RCA cleaning) were examined. The etching rate of Si1−xGex became larger with increasing Ge ratio (X). Temperature dependence of the etching rate was studied and the etching rate was large at high temperatures. However, no obvious difference was observed in the temperature dependence of Si1−xGex etching rate at different Ge ratio (X). A surface morhology degradation after RCA cleaning was observed at high Ge ratio (X). A stoichiometry change of Si1−xGex surface after RCA cleaning was observed by x-ray photoelectron spectroscopy (XPS). The etching rate increase and the surface morphology degradation are thought to be due to the rapid etching of Ge atoms at the top surface layer.
A high-dielectric-constant material was applied to a practical stacked DRAM capacitor for the first time. A large unit area capacitance (40fF/pm2) and a low leakage current (<10-'A/cm2) have been realized by the combination of a thin (B%Sr-)TiO, film having an equivalent SiO, thickness of 8kand a P O a capacitor electrode. These characteristics show that this storage capacitor is quite promising for 256M DRAM cells.
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