Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time

Abstract

In this paper we propose a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics. For main-mode bits, leakage current can be attributed to junction thermal-generation leakage current. For tail-mode bits, it is found for the first time that Gate-Induced Drain Leakage (GIDL) current has a dominant impact. The root cause is electric field enhancement caused by metal precipitates located at the gate-drain overlap region.

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

“…This is due to various leakage mechanisms by which charge can disperse: e.g., subthreshold leakage [56] and gate-induced drain leakage [57]. Eventually, the cell's charge-level would deviate beyond the noise margin, causing it to lose data -in other words, a cell has only a limited retention time.…”

Temperature and drain voltage dependence of gate-induced drain leakage

“…It has also been reported that GIDL is the major leakage mechanism that limits DRAM data retention [2]. Fig.…”

Method of activation energy analysis and application to individual cells of 256Mb DRAM in 110nm technology

“…Based on simulations, pure thermal G-R-current from traps of Au and Zn has been suggested in [3], whereas [2] intimates a thermionic field enhanced mechanism (TFE) originating from the junction area. Finally [4,5] assert trap assisted GIDL as the most important path in the tail distribution of modern DRAM.…”

“…Many researchers have investigated the retention tail regarding dominant paths and mechanisms, e.g. [2][3][4][5]. Based on simulations, pure thermal G-R-current from traps of Au and Zn has been suggested in [3], whereas [2] intimates a thermionic field enhanced mechanism (TFE) originating from the junction area.…”