In keeping up with the tightening overall budget in lithography, metrology requirements have reached a deep subnanometer level [1]. This drives the need for clean metrology (resolution and precision). Results have been published of a thorough investigation of a scatterometry-based platform from ASML [7], showing promising results on resolution, precision, and tool matching for overlay, CD and focus [2 -6].But overall requirements are so extreme that all measures must be taken in order to meet them. In light of this, in addition to above-mentioned need for resolution and precision, the speed and sophistication in communication between litho and metrology (feedback control) are also becoming increasingly crucial. An effective sampling strategy for metrology plays a big role in order to achieve this.This study discusses results from above mentioned scatterometry-based platform in light of sampling optimization. For overlay, various sampling schemes (dense / sparse combinations as well as inter and intra field schemes) were used on many production lots. The effectiveness of such sample schemes were studied to reveal an ideal sampling scheme that can result in 0.5nm to 1nm gain in overlay control (compare to today's practice). Moreover, cycle time contribution of metrology (at litho) in overall cycle time of a full process flow was investigated and quantified with the concept of integrated metrology. Results indicate a cycle time reduction per layer (if an integrated concept is used) of 3 to 5 hours, which can easily add up to several days of total cycle time reduction for a fab. BACKGROUNDFueled by the desire for a better overlay correction, the drive towards increased sampling in metrology continues. However, there is a trade-off between the overlay correction accuracy and metrology time: a primary concern when selecting an overlay sampling plan is the balance between accuracy and throughput [9]. Industry has adopted many ways to improve overlay by various correction schemes like linear and high-order process corrections (HOPC), correction per-exposure (CPE) as well as in-die high-order corrections (iHOPC). Much work is done on this topic of sampling scheme and efficiency in order to capture the industry trend towards the transition from stepper to scanner, 200 mm to 300 mm wafer, the transition from linear to high order (including both inter-field and intra-field) overlay control, and the transition to dual patterning lithography (DPL) processes [8,9,10,11]. MOTIVATIONTotal overlay error budget consists of four major contribution categories: scanner, process, metrology and mask contributions [12]. Around 50% or more of this contribution comes from process (etch, CMP etc.); in other words, process remains the major contributor to overlay. All these effects need to be considered in order to achieve the most optimum sampling. There are probably three ways to capture these effects on overlay in light of achieving an optimum sampling for overlay control (individually or some combination of any of these three):(a) Measur...