A capillary pen drawing technique, developed as a new patterning methodology for the large-area patterning and fabrication of organic electronics, provides several advantages over conventional approaches: the method is simple and versatile, there are no restrictions on the patterning shapes that could be produced, and the method can be tailored to a variety of substrates.

The surface functionality of the gate dielectrics is one of the important variables to have a huge impact on the electrical performance of organic field-effect transistors (OFETs). Here, we describe the impact of energetically engineered dielectrics on charge transport in vacuum-deposited 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) thin films for eventually realizing high-performance OFETs. A variety of self-assembled monolayers (SAMs) bearing amino, methyl, phenyl (PTS), or fluoro end groups were introduced onto the SiO 2 dielectric surfaces to design energetically engineered surfaces that can be used to explore the impact of surface functionalities at a TIPS-pentacene/gate dielectric interface. The solvent-free vacuum deposition of TIPSpentacene was used to exclude solution-processing effects resulting from fluid flows and solvent drying processes. The TIPS-pentacene layer on the PTS-SAM yielded the best morphological and crystalline structures, which directly enhanced the electrical properties, exhibiting field-effect mobilities as high as 0.18 cm 2 /(V s). Furthermore, the hysteresis, turn-on voltage, and threshold voltage were correlated with the surface potentials of various SAM-dielectrics. We believe that systematic investigation of the energetically engineered dielectrics presented here can provide a meaningful step toward optimizing the organic semiconductor/dielectric interface, thereby implementing flexible and high-performance OFETs.

Printing technologies are instrumental to the fabrication of low‐cost lightweight flexible electronic devices and circuits, which are necessary to produce wearable electronic applications. However, attaining fully printed devices on flexible films over large areas has typically been a challenge. Here, the fabrication of fully drawn all‐organic field‐effect transistor (FET) arrays on mechanically flexible substrates using a capillary‐pen printing method is demonstrated. A highly crystalline organic semiconductor (active layer), a smooth insulating polymer (dielectric layer), and a conducting polymer (source, drain, and gate electrodes) are deposited from solution sequentially. The bottom‐gate bottom‐contact FETs drawn onto flexible substrates exhibit superior field‐effect mobilities of up to 0.54 cm2 V−1 s−1, good reproducibility, operational stability, and mechanical bendability. Furthermore, to emphasize the methodological advantages of the capillary‐pen printing, an organic FET (OFET) array on a curvilinear substrate of a plastic straw and the repairing concept for a broken electrical circuit are demonstrated. These results indicate that capillary pen printing shows promise as a manufacturing technique for a wide range of large‐area electronic applications.

Research into printing techniques has received special attention for the commercialization of cost-efficient organic electronics. Here, we have developed a capillary pen printing technique to realize a large-area pattern array of organic transistors and systematically investigated self-organization behavior of printed soluble organic semiconductor ink. The capillary pen-printed deposits of organic semiconductor, 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS_PEN), was well-optimized in terms of morphological and microstructural properties by using ink with mixed solvents of chlorobenzene (CB) and 1,2-dichlorobenzene (DCB). Especially, a 1:1 solvent ratio results in the best transistor performances. This result is attributed to the unique evaporation characteristics of the TIPS_PEN deposits where fast evaporation of CB induces a morphological evolution at the initial printed position, and the remaining DCB with slow evaporation rate offers a favorable crystal evolution at the pinned position. Finally, a large-area transistor array was facilely fabricated by drawing organic electrodes and active layers with a versatile capillary pen. Our approach provides an efficient printing technique for fabricating large-area arrays of organic electronics and further suggests a methodology to enhance their performances by microstructural control of the printed organic semiconducting deposits.

Charge traps in polymer gate dielectrics determine the electrical stability of organic field-effect transistors (OFETs), and polar alkoxy groups are well-known extrinsic charge traps. However, the actual location of intrinsic charge traps in nonpolar polymer gate dielectrics has been poorly understood yet. Here, we demonstrate that the skeletal structure of polymer chain plays an important role in determining the electrical stability. To verify it, we prepared linear and branched polystyrene (l-PS and b-PS) and blended them, in which branched segments provide much larger free volume than the other segments. The current-insulating performance and field-effect mobility increased with decease of b-PS portion. In particular, the bias-stress stability was remarkably varied according to the change of b-PS portion even though all measurements excluded reactive components such as oxygen and water; the increase of b-PS resulted in time-dependent decay of mobility and threshold voltage under bias stress. This indicates that the branched segments in b-PS provide intrinsic and metastable charge trap sites. Our result suggests that the skeletal structure of polymeric chains in gate dielectric is one of the important factors affecting intrinsic long-term operational stability of OFET devices.