Many studies point to the difficulty of scaling existing computer architectures to meet the needs of an exascale system (i.e., capable of executing 10 18 floating-point operations per second), consuming no more than 20 MW in power, by around the year 2020. This paper outlines a new architecture, the Active Memory Cube, which reduces the energy of computation significantly by performing computation in the memory module, rather than moving data through large memory hierarchies to the processor core. The architecture leverages a commercially demonstrated 3D memory stack called the Hybrid Memory Cube, placing sophisticated computational elements on the logic layer below its stack of dynamic random-access memory (DRAM) dies. The paper also describes an Active Memory Cube tuned to the requirements of a scientific exascale system. The computational elements have a vector architecture and are capable of performing a comprehensive set of floating-point and integer instructions, predicated operations, and gather-scatter accesses across memory in the Cube. The paper outlines the software infrastructure used to develop applications and to evaluate the architecture, and describes results of experiments on application kernels, along with performance and power projections.

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As supercomputers are shifting from peta-scale to exa-scale, computers with accelerators such as GPUs, MICs and FPGAs have become one of the big trends of supercomputer because of their low energy consumption and high density. Now IBM's POWER processor has quite new power, Nvidia's Tesla GPU brings huge computational capability. It is important for us to understand how this new POWER+GPU environment brings power to the actual applications in the early stage. We implemented Wilson-Dirac operator and BiCGStab solver using CUDA7.0 on the POWER+GPU cluster and evaluated the performance.

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